43 lines · c
1/* SPDX-License-Identifier: GPL-2.0+2 *3 * Copyright (C) 2020 Renesas Electronics Corp.4 */5#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__6#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* r8a7742 CPG Core Clocks */11#define R8A7742_CLK_Z 012#define R8A7742_CLK_Z2 113#define R8A7742_CLK_ZG 214#define R8A7742_CLK_ZTR 315#define R8A7742_CLK_ZTRD2 416#define R8A7742_CLK_ZT 517#define R8A7742_CLK_ZX 618#define R8A7742_CLK_ZS 719#define R8A7742_CLK_HP 820#define R8A7742_CLK_B 921#define R8A7742_CLK_LB 1022#define R8A7742_CLK_P 1123#define R8A7742_CLK_CL 1224#define R8A7742_CLK_M2 1325#define R8A7742_CLK_ZB3 1426#define R8A7742_CLK_ZB3D2 1527#define R8A7742_CLK_DDR 1628#define R8A7742_CLK_SDH 1729#define R8A7742_CLK_SD0 1830#define R8A7742_CLK_SD1 1931#define R8A7742_CLK_SD2 2032#define R8A7742_CLK_SD3 2133#define R8A7742_CLK_MMC0 2234#define R8A7742_CLK_MMC1 2335#define R8A7742_CLK_MP 2436#define R8A7742_CLK_QSPI 2537#define R8A7742_CLK_CP 2638#define R8A7742_CLK_RCAN 2739#define R8A7742_CLK_R 2840#define R8A7742_CLK_OSC 2941 42#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */43