40 lines · c
1/* SPDX-License-Identifier: GPL-2.0+2 *3 * Copyright (C) 2016 Cogent Embedded Inc.4 */5#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__6#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* r8a7743 CPG Core Clocks */11#define R8A7743_CLK_Z 012#define R8A7743_CLK_ZG 113#define R8A7743_CLK_ZTR 214#define R8A7743_CLK_ZTRD2 315#define R8A7743_CLK_ZT 416#define R8A7743_CLK_ZX 517#define R8A7743_CLK_ZS 618#define R8A7743_CLK_HP 719#define R8A7743_CLK_B 920#define R8A7743_CLK_LB 1021#define R8A7743_CLK_P 1122#define R8A7743_CLK_CL 1223#define R8A7743_CLK_M2 1324#define R8A7743_CLK_ZB3 1525#define R8A7743_CLK_ZB3D2 1626#define R8A7743_CLK_DDR 1727#define R8A7743_CLK_SDH 1828#define R8A7743_CLK_SD0 1929#define R8A7743_CLK_SD2 2030#define R8A7743_CLK_SD3 2131#define R8A7743_CLK_MMC0 2232#define R8A7743_CLK_MP 2333#define R8A7743_CLK_QSPI 2634#define R8A7743_CLK_CP 2735#define R8A7743_CLK_RCAN 2836#define R8A7743_CLK_R 2937#define R8A7743_CLK_OSC 3038 39#endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */40