41 lines · c
1/* SPDX-License-Identifier: GPL-2.0+2 *3 * Copyright (C) 2016 Cogent Embedded Inc.4 */5#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__6#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* r8a7745 CPG Core Clocks */11#define R8A7745_CLK_Z2 012#define R8A7745_CLK_ZG 113#define R8A7745_CLK_ZTR 214#define R8A7745_CLK_ZTRD2 315#define R8A7745_CLK_ZT 416#define R8A7745_CLK_ZX 517#define R8A7745_CLK_ZS 618#define R8A7745_CLK_HP 719#define R8A7745_CLK_B 920#define R8A7745_CLK_LB 1021#define R8A7745_CLK_P 1122#define R8A7745_CLK_CL 1223#define R8A7745_CLK_CP 1324#define R8A7745_CLK_M2 1425#define R8A7745_CLK_ZB3 1626#define R8A7745_CLK_ZB3D2 1727#define R8A7745_CLK_DDR 1828#define R8A7745_CLK_SDH 1929#define R8A7745_CLK_SD0 2030#define R8A7745_CLK_SD2 2131#define R8A7745_CLK_SD3 2232#define R8A7745_CLK_MMC0 2333#define R8A7745_CLK_MP 2434#define R8A7745_CLK_QSPI 2535#define R8A7745_CLK_CPEX 2636#define R8A7745_CLK_RCAN 2737#define R8A7745_CLK_R 2838#define R8A7745_CLK_OSC 2939 40#endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */41