37 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright (C) 2018 Renesas Electronics Corp.4 */5#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__6#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* r8a77470 CPG Core Clocks */11#define R8A77470_CLK_Z2 012#define R8A77470_CLK_ZTR 113#define R8A77470_CLK_ZTRD2 214#define R8A77470_CLK_ZT 315#define R8A77470_CLK_ZX 416#define R8A77470_CLK_ZS 517#define R8A77470_CLK_HP 618#define R8A77470_CLK_B 719#define R8A77470_CLK_LB 820#define R8A77470_CLK_P 921#define R8A77470_CLK_CL 1022#define R8A77470_CLK_CP 1123#define R8A77470_CLK_M2 1224#define R8A77470_CLK_ZB3 1325#define R8A77470_CLK_SDH 1426#define R8A77470_CLK_SD0 1527#define R8A77470_CLK_SD1 1628#define R8A77470_CLK_SD2 1729#define R8A77470_CLK_MP 1830#define R8A77470_CLK_QSPI 1931#define R8A77470_CLK_CPEX 2032#define R8A77470_CLK_RCAN 2133#define R8A77470_CLK_R 2234#define R8A77470_CLK_OSC 2335 36#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */37