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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright (C) 2018 Renesas Electronics Corp.4 */5#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__6#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* r8a774a1 CPG Core Clocks */11#define R8A774A1_CLK_Z 012#define R8A774A1_CLK_Z2 113#define R8A774A1_CLK_ZG 214#define R8A774A1_CLK_ZTR 315#define R8A774A1_CLK_ZTRD2 416#define R8A774A1_CLK_ZT 517#define R8A774A1_CLK_ZX 618#define R8A774A1_CLK_S0D1 719#define R8A774A1_CLK_S0D2 820#define R8A774A1_CLK_S0D3 921#define R8A774A1_CLK_S0D4 1022#define R8A774A1_CLK_S0D6 1123#define R8A774A1_CLK_S0D8 1224#define R8A774A1_CLK_S0D12 1325#define R8A774A1_CLK_S1D2 1426#define R8A774A1_CLK_S1D4 1527#define R8A774A1_CLK_S2D1 1628#define R8A774A1_CLK_S2D2 1729#define R8A774A1_CLK_S2D4 1830#define R8A774A1_CLK_S3D1 1931#define R8A774A1_CLK_S3D2 2032#define R8A774A1_CLK_S3D4 2133#define R8A774A1_CLK_LB 2234#define R8A774A1_CLK_CL 2335#define R8A774A1_CLK_ZB3 2436#define R8A774A1_CLK_ZB3D2 2537#define R8A774A1_CLK_ZB3D4 2638#define R8A774A1_CLK_CR 2739#define R8A774A1_CLK_CRD2 2840#define R8A774A1_CLK_SD0H 2941#define R8A774A1_CLK_SD0 3042#define R8A774A1_CLK_SD1H 3143#define R8A774A1_CLK_SD1 3244#define R8A774A1_CLK_SD2H 3345#define R8A774A1_CLK_SD2 3446#define R8A774A1_CLK_SD3H 3547#define R8A774A1_CLK_SD3 3648#define R8A774A1_CLK_RPC 3749#define R8A774A1_CLK_RPCD2 3850#define R8A774A1_CLK_MSO 3951#define R8A774A1_CLK_HDMI 4052#define R8A774A1_CLK_CSI0 4153#define R8A774A1_CLK_CP 4254#define R8A774A1_CLK_CPEX 4355#define R8A774A1_CLK_R 4456#define R8A774A1_CLK_OSC 4557#define R8A774A1_CLK_CANFD 4658 59#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */60