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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright (C) 2019 Renesas Electronics Corp.4 */5#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__6#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* r8a774b1 CPG Core Clocks */11#define R8A774B1_CLK_Z 012#define R8A774B1_CLK_ZG 113#define R8A774B1_CLK_ZTR 214#define R8A774B1_CLK_ZTRD2 315#define R8A774B1_CLK_ZT 416#define R8A774B1_CLK_ZX 517#define R8A774B1_CLK_S0D1 618#define R8A774B1_CLK_S0D2 719#define R8A774B1_CLK_S0D3 820#define R8A774B1_CLK_S0D4 921#define R8A774B1_CLK_S0D6 1022#define R8A774B1_CLK_S0D8 1123#define R8A774B1_CLK_S0D12 1224#define R8A774B1_CLK_S1D2 1325#define R8A774B1_CLK_S1D4 1426#define R8A774B1_CLK_S2D1 1527#define R8A774B1_CLK_S2D2 1628#define R8A774B1_CLK_S2D4 1729#define R8A774B1_CLK_S3D1 1830#define R8A774B1_CLK_S3D2 1931#define R8A774B1_CLK_S3D4 2032#define R8A774B1_CLK_LB 2133#define R8A774B1_CLK_CL 2234#define R8A774B1_CLK_ZB3 2335#define R8A774B1_CLK_ZB3D2 2436#define R8A774B1_CLK_CR 2537#define R8A774B1_CLK_DDR 2638#define R8A774B1_CLK_SD0H 2739#define R8A774B1_CLK_SD0 2840#define R8A774B1_CLK_SD1H 2941#define R8A774B1_CLK_SD1 3042#define R8A774B1_CLK_SD2H 3143#define R8A774B1_CLK_SD2 3244#define R8A774B1_CLK_SD3H 3345#define R8A774B1_CLK_SD3 3446#define R8A774B1_CLK_RPC 3547#define R8A774B1_CLK_RPCD2 3648#define R8A774B1_CLK_MSO 3749#define R8A774B1_CLK_HDMI 3850#define R8A774B1_CLK_CSI0 3951#define R8A774B1_CLK_CP 4052#define R8A774B1_CLK_CPEX 4153#define R8A774B1_CLK_R 4254#define R8A774B1_CLK_OSC 4355#define R8A774B1_CLK_CANFD 4456 57#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */58