49 lines · c
1/* SPDX-License-Identifier: GPL-2.0+2 *3 * Copyright (C) 2015 Renesas Electronics Corp.4 */5 6#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__7#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__8 9#include <dt-bindings/clock/renesas-cpg-mssr.h>10 11/* r8a7790 CPG Core Clocks */12#define R8A7790_CLK_Z 013#define R8A7790_CLK_Z2 114#define R8A7790_CLK_ZG 215#define R8A7790_CLK_ZTR 316#define R8A7790_CLK_ZTRD2 417#define R8A7790_CLK_ZT 518#define R8A7790_CLK_ZX 619#define R8A7790_CLK_ZS 720#define R8A7790_CLK_HP 821#define R8A7790_CLK_I 922#define R8A7790_CLK_B 1023#define R8A7790_CLK_LB 1124#define R8A7790_CLK_P 1225#define R8A7790_CLK_CL 1326#define R8A7790_CLK_M2 1427#define R8A7790_CLK_ADSP 1528#define R8A7790_CLK_IMP 1629#define R8A7790_CLK_ZB3 1730#define R8A7790_CLK_ZB3D2 1831#define R8A7790_CLK_DDR 1932#define R8A7790_CLK_SDH 2033#define R8A7790_CLK_SD0 2134#define R8A7790_CLK_SD1 2235#define R8A7790_CLK_SD2 2336#define R8A7790_CLK_SD3 2437#define R8A7790_CLK_MMC0 2538#define R8A7790_CLK_MMC1 2639#define R8A7790_CLK_MP 2740#define R8A7790_CLK_SSP 2841#define R8A7790_CLK_SSPRS 2942#define R8A7790_CLK_QSPI 3043#define R8A7790_CLK_CP 3144#define R8A7790_CLK_RCAN 3245#define R8A7790_CLK_R 3346#define R8A7790_CLK_OSC 3447 48#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */49