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1/* SPDX-License-Identifier: GPL-2.0+2 *3 * Copyright (C) 2015 Renesas Electronics Corp.4 */5 6#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__7#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__8 9#include <dt-bindings/clock/renesas-cpg-mssr.h>10 11/* r8a7792 CPG Core Clocks */12#define R8A7792_CLK_Z 013#define R8A7792_CLK_ZG 114#define R8A7792_CLK_ZTR 215#define R8A7792_CLK_ZTRD2 316#define R8A7792_CLK_ZT 417#define R8A7792_CLK_ZX 518#define R8A7792_CLK_ZS 619#define R8A7792_CLK_HP 720#define R8A7792_CLK_I 821#define R8A7792_CLK_B 922#define R8A7792_CLK_LB 1023#define R8A7792_CLK_P 1124#define R8A7792_CLK_CL 1225#define R8A7792_CLK_M2 1326#define R8A7792_CLK_IMP 1427#define R8A7792_CLK_ZB3 1528#define R8A7792_CLK_ZB3D2 1629#define R8A7792_CLK_DDR 1730#define R8A7792_CLK_SD 1831#define R8A7792_CLK_MP 1932#define R8A7792_CLK_QSPI 2033#define R8A7792_CLK_CP 2134#define R8A7792_CLK_CPEX 2235#define R8A7792_CLK_RCAN 2336#define R8A7792_CLK_R 2437#define R8A7792_CLK_OSC 2538 39#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */40