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1/* SPDX-License-Identifier: GPL-2.0+2 *3 * Copyright (C) 2015 Renesas Electronics Corp.4 */5#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__6#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* r8a7795 CPG Core Clocks */11#define R8A7795_CLK_Z 012#define R8A7795_CLK_Z2 113#define R8A7795_CLK_ZR 214#define R8A7795_CLK_ZG 315#define R8A7795_CLK_ZTR 416#define R8A7795_CLK_ZTRD2 517#define R8A7795_CLK_ZT 618#define R8A7795_CLK_ZX 719#define R8A7795_CLK_S0D1 820#define R8A7795_CLK_S0D4 921#define R8A7795_CLK_S1D1 1022#define R8A7795_CLK_S1D2 1123#define R8A7795_CLK_S1D4 1224#define R8A7795_CLK_S2D1 1325#define R8A7795_CLK_S2D2 1426#define R8A7795_CLK_S2D4 1527#define R8A7795_CLK_S3D1 1628#define R8A7795_CLK_S3D2 1729#define R8A7795_CLK_S3D4 1830#define R8A7795_CLK_LB 1931#define R8A7795_CLK_CL 2032#define R8A7795_CLK_ZB3 2133#define R8A7795_CLK_ZB3D2 2234#define R8A7795_CLK_CR 2335#define R8A7795_CLK_CRD2 2436#define R8A7795_CLK_SD0H 2537#define R8A7795_CLK_SD0 2638#define R8A7795_CLK_SD1H 2739#define R8A7795_CLK_SD1 2840#define R8A7795_CLK_SD2H 2941#define R8A7795_CLK_SD2 3042#define R8A7795_CLK_SD3H 3143#define R8A7795_CLK_SD3 3244#define R8A7795_CLK_SSP2 3345#define R8A7795_CLK_SSP1 3446#define R8A7795_CLK_SSPRS 3547#define R8A7795_CLK_RPC 3648#define R8A7795_CLK_RPCD2 3749#define R8A7795_CLK_MSO 3850#define R8A7795_CLK_CANFD 3951#define R8A7795_CLK_HDMI 4052#define R8A7795_CLK_CSI0 4153/* CLK_CSIREF was removed */54#define R8A7795_CLK_CP 4355#define R8A7795_CLK_CPEX 4456#define R8A7795_CLK_R 4557#define R8A7795_CLK_OSC 4658 59/* r8a7795 ES2.0 CPG Core Clocks */60#define R8A7795_CLK_S0D2 4761#define R8A7795_CLK_S0D3 4862#define R8A7795_CLK_S0D6 4963#define R8A7795_CLK_S0D8 5064#define R8A7795_CLK_S0D12 5165 66#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */67