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1/* SPDX-License-Identifier: GPL-2.0+2 *3 * Copyright (C) 2016 Renesas Electronics Corp.4 */5#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__6#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* r8a7796 CPG Core Clocks */11#define R8A7796_CLK_Z 012#define R8A7796_CLK_Z2 113#define R8A7796_CLK_ZR 214#define R8A7796_CLK_ZG 315#define R8A7796_CLK_ZTR 416#define R8A7796_CLK_ZTRD2 517#define R8A7796_CLK_ZT 618#define R8A7796_CLK_ZX 719#define R8A7796_CLK_S0D1 820#define R8A7796_CLK_S0D2 921#define R8A7796_CLK_S0D3 1022#define R8A7796_CLK_S0D4 1123#define R8A7796_CLK_S0D6 1224#define R8A7796_CLK_S0D8 1325#define R8A7796_CLK_S0D12 1426#define R8A7796_CLK_S1D1 1527#define R8A7796_CLK_S1D2 1628#define R8A7796_CLK_S1D4 1729#define R8A7796_CLK_S2D1 1830#define R8A7796_CLK_S2D2 1931#define R8A7796_CLK_S2D4 2032#define R8A7796_CLK_S3D1 2133#define R8A7796_CLK_S3D2 2234#define R8A7796_CLK_S3D4 2335#define R8A7796_CLK_LB 2436#define R8A7796_CLK_CL 2537#define R8A7796_CLK_ZB3 2638#define R8A7796_CLK_ZB3D2 2739#define R8A7796_CLK_ZB3D4 2840#define R8A7796_CLK_CR 2941#define R8A7796_CLK_CRD2 3042#define R8A7796_CLK_SD0H 3143#define R8A7796_CLK_SD0 3244#define R8A7796_CLK_SD1H 3345#define R8A7796_CLK_SD1 3446#define R8A7796_CLK_SD2H 3547#define R8A7796_CLK_SD2 3648#define R8A7796_CLK_SD3H 3749#define R8A7796_CLK_SD3 3850#define R8A7796_CLK_SSP2 3951#define R8A7796_CLK_SSP1 4052#define R8A7796_CLK_SSPRS 4153#define R8A7796_CLK_RPC 4254#define R8A7796_CLK_RPCD2 4355#define R8A7796_CLK_MSO 4456#define R8A7796_CLK_CANFD 4557#define R8A7796_CLK_HDMI 4658#define R8A7796_CLK_CSI0 4759/* CLK_CSIREF was removed */60#define R8A7796_CLK_CP 4961#define R8A7796_CLK_CPEX 5062#define R8A7796_CLK_R 5163#define R8A7796_CLK_OSC 5264 65#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */66