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1/* SPDX-License-Identifier: GPL-2.0+2 *3 * Copyright (C) 2016 Renesas Electronics Corp.4 * Copyright (C) 2017 Cogent Embedded, Inc.5 */6#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__7#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__8 9#include <dt-bindings/clock/renesas-cpg-mssr.h>10 11/* r8a77970 CPG Core Clocks */12#define R8A77970_CLK_Z2 013#define R8A77970_CLK_ZR 114#define R8A77970_CLK_ZTR 215#define R8A77970_CLK_ZTRD2 316#define R8A77970_CLK_ZT 417#define R8A77970_CLK_ZX 518#define R8A77970_CLK_S1D1 619#define R8A77970_CLK_S1D2 720#define R8A77970_CLK_S1D4 821#define R8A77970_CLK_S2D1 922#define R8A77970_CLK_S2D2 1023#define R8A77970_CLK_S2D4 1124#define R8A77970_CLK_LB 1225#define R8A77970_CLK_CL 1326#define R8A77970_CLK_ZB3 1427#define R8A77970_CLK_ZB3D2 1528#define R8A77970_CLK_DDR 1629#define R8A77970_CLK_CR 1730#define R8A77970_CLK_CRD2 1831#define R8A77970_CLK_SD0H 1932#define R8A77970_CLK_SD0 2033#define R8A77970_CLK_RPC 2134#define R8A77970_CLK_RPCD2 2235#define R8A77970_CLK_MSO 2336#define R8A77970_CLK_CANFD 2437#define R8A77970_CLK_CSI0 2538#define R8A77970_CLK_FRAY 2639#define R8A77970_CLK_CP 2740#define R8A77970_CLK_CPEX 2841#define R8A77970_CLK_R 2942#define R8A77970_CLK_OSC 3043 44#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */45