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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Copyright (C) 2018 Renesas Electronics Corp.4 * Copyright (C) 2018 Cogent Embedded, Inc.5 */6#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__7#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__8 9#include <dt-bindings/clock/renesas-cpg-mssr.h>10 11/* r8a77980 CPG Core Clocks */12#define R8A77980_CLK_Z2 013#define R8A77980_CLK_ZR 114#define R8A77980_CLK_ZTR 215#define R8A77980_CLK_ZTRD2 316#define R8A77980_CLK_ZT 417#define R8A77980_CLK_ZX 518#define R8A77980_CLK_S0D1 619#define R8A77980_CLK_S0D2 720#define R8A77980_CLK_S0D3 821#define R8A77980_CLK_S0D4 922#define R8A77980_CLK_S0D6 1023#define R8A77980_CLK_S0D12 1124#define R8A77980_CLK_S0D24 1225#define R8A77980_CLK_S1D1 1326#define R8A77980_CLK_S1D2 1427#define R8A77980_CLK_S1D4 1528#define R8A77980_CLK_S2D1 1629#define R8A77980_CLK_S2D2 1730#define R8A77980_CLK_S2D4 1831#define R8A77980_CLK_S3D1 1932#define R8A77980_CLK_S3D2 2033#define R8A77980_CLK_S3D4 2134#define R8A77980_CLK_LB 2235#define R8A77980_CLK_CL 2336#define R8A77980_CLK_ZB3 2437#define R8A77980_CLK_ZB3D2 2538#define R8A77980_CLK_ZB3D4 2639#define R8A77980_CLK_SD0H 2740#define R8A77980_CLK_SD0 2841#define R8A77980_CLK_RPC 2942#define R8A77980_CLK_RPCD2 3043#define R8A77980_CLK_MSO 3144#define R8A77980_CLK_CANFD 3245#define R8A77980_CLK_CSI0 3346#define R8A77980_CLK_CP 3447#define R8A77980_CLK_CPEX 3548#define R8A77980_CLK_R 3649#define R8A77980_CLK_OSC 3750 51#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */52