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1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */2/*3 * Copyright (C) 2021 Renesas Electronics Corp.4 */5#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__6#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* r8a779f0 CPG Core Clocks */11 12#define R8A779F0_CLK_ZX 013#define R8A779F0_CLK_ZS 114#define R8A779F0_CLK_ZT 215#define R8A779F0_CLK_ZTR 316#define R8A779F0_CLK_S0D2 417#define R8A779F0_CLK_S0D3 518#define R8A779F0_CLK_S0D4 619#define R8A779F0_CLK_S0D2_MM 720#define R8A779F0_CLK_S0D3_MM 821#define R8A779F0_CLK_S0D4_MM 922#define R8A779F0_CLK_S0D2_RT 1023#define R8A779F0_CLK_S0D3_RT 1124#define R8A779F0_CLK_S0D4_RT 1225#define R8A779F0_CLK_S0D6_RT 1326#define R8A779F0_CLK_S0D3_PER 1427#define R8A779F0_CLK_S0D6_PER 1528#define R8A779F0_CLK_S0D12_PER 1629#define R8A779F0_CLK_S0D24_PER 1730#define R8A779F0_CLK_S0D2_HSC 1831#define R8A779F0_CLK_S0D3_HSC 1932#define R8A779F0_CLK_S0D4_HSC 2033#define R8A779F0_CLK_S0D6_HSC 2134#define R8A779F0_CLK_S0D12_HSC 2235#define R8A779F0_CLK_S0D2_CC 2336#define R8A779F0_CLK_CL 2437#define R8A779F0_CLK_CL16M 2538#define R8A779F0_CLK_CL16M_MM 2639#define R8A779F0_CLK_CL16M_RT 2740#define R8A779F0_CLK_CL16M_PER 2841#define R8A779F0_CLK_CL16M_HSC 2942#define R8A779F0_CLK_Z0 3043#define R8A779F0_CLK_Z1 3144#define R8A779F0_CLK_ZB3 3245#define R8A779F0_CLK_ZB3D2 3346#define R8A779F0_CLK_ZB3D4 3447#define R8A779F0_CLK_SD0H 3548#define R8A779F0_CLK_SD0 3649#define R8A779F0_CLK_RPC 3750#define R8A779F0_CLK_RPCD2 3851#define R8A779F0_CLK_MSO 3952#define R8A779F0_CLK_SASYNCRT 4053#define R8A779F0_CLK_SASYNCPERD1 4154#define R8A779F0_CLK_SASYNCPERD2 4255#define R8A779F0_CLK_SASYNCPERD4 4356#define R8A779F0_CLK_DBGSOC_HSC 4457#define R8A779F0_CLK_RSW2 4558#define R8A779F0_CLK_OSC 4659#define R8A779F0_CLK_ZR 4760#define R8A779F0_CLK_CPEX 4861#define R8A779F0_CLK_CBFUSA 4962#define R8A779F0_CLK_R 5063 64#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */65