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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * R9A06G032 sysctrl IDs4 *5 * Copyright (C) 2018 Renesas Electronics Europe Limited6 *7 * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>8 */9 10#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__11#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__12 13#define R9A06G032_CLK_PLL_USB 114#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */15#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */16#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */17#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */18#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */19#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */20#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */21#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */22#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */23#define R9A06G032_CLK_25_PG4 2624#define R9A06G032_CLK_25_PG5 2725#define R9A06G032_CLK_25_PG6 2826#define R9A06G032_CLK_25_PG7 2927#define R9A06G032_CLK_25_PG8 3028#define R9A06G032_CLK_ADC 3129#define R9A06G032_CLK_ECAT100 3230#define R9A06G032_CLK_HSR100 3331#define R9A06G032_CLK_I2C0 3432#define R9A06G032_CLK_I2C1 3533#define R9A06G032_CLK_MII_REF 3634#define R9A06G032_CLK_NAND 3735#define R9A06G032_CLK_NOUSBP2_PG6 3836#define R9A06G032_CLK_P1_PG2 3937#define R9A06G032_CLK_P1_PG3 4038#define R9A06G032_CLK_P1_PG4 4139#define R9A06G032_CLK_P4_PG3 4240#define R9A06G032_CLK_P4_PG4 4341#define R9A06G032_CLK_P6_PG1 4442#define R9A06G032_CLK_P6_PG2 4543#define R9A06G032_CLK_P6_PG3 4644#define R9A06G032_CLK_P6_PG4 4745#define R9A06G032_CLK_PCI_USB 4846#define R9A06G032_CLK_QSPI0 4947#define R9A06G032_CLK_QSPI1 5048#define R9A06G032_CLK_RGMII_REF 5149#define R9A06G032_CLK_RMII_REF 5250#define R9A06G032_CLK_SDIO0 5351#define R9A06G032_CLK_SDIO1 5452#define R9A06G032_CLK_SERCOS100 5553#define R9A06G032_CLK_SLCD 5654#define R9A06G032_CLK_SPI0 5755#define R9A06G032_CLK_SPI1 5856#define R9A06G032_CLK_SPI2 5957#define R9A06G032_CLK_SPI3 6058#define R9A06G032_CLK_SPI4 6159#define R9A06G032_CLK_SPI5 6260#define R9A06G032_CLK_SWITCH 6361#define R9A06G032_HCLK_ECAT125 6562#define R9A06G032_HCLK_PINCONFIG 6663#define R9A06G032_HCLK_SERCOS 6764#define R9A06G032_HCLK_SGPIO2 6865#define R9A06G032_HCLK_SGPIO3 6966#define R9A06G032_HCLK_SGPIO4 7067#define R9A06G032_HCLK_TIMER0 7168#define R9A06G032_HCLK_TIMER1 7269#define R9A06G032_HCLK_USBF 7370#define R9A06G032_HCLK_USBH 7471#define R9A06G032_HCLK_USBPM 7572#define R9A06G032_CLK_48_PG_F 7673#define R9A06G032_CLK_48_PG4 7774#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */75#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */76#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */77#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */78#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */79#define R9A06G032_HCLK_CAN0 8580#define R9A06G032_HCLK_CAN1 8681#define R9A06G032_HCLK_DELTASIGMA 8782#define R9A06G032_HCLK_PWMPTO 8883#define R9A06G032_HCLK_RSV 8984#define R9A06G032_HCLK_SGPIO0 9085#define R9A06G032_HCLK_SGPIO1 9186#define R9A06G032_RTOS_MDC 9287#define R9A06G032_CLK_CM3 9388#define R9A06G032_CLK_DDRC 9489#define R9A06G032_CLK_ECAT25 9590#define R9A06G032_CLK_HSR50 9691#define R9A06G032_CLK_HW_RTOS 9792#define R9A06G032_CLK_SERCOS50 9893#define R9A06G032_HCLK_ADC 9994#define R9A06G032_HCLK_CM3 10095#define R9A06G032_HCLK_CRYPTO_EIP150 10196#define R9A06G032_HCLK_CRYPTO_EIP93 10297#define R9A06G032_HCLK_DDRC 10398#define R9A06G032_HCLK_DMA0 10499#define R9A06G032_HCLK_DMA1 105100#define R9A06G032_HCLK_GMAC0 106101#define R9A06G032_HCLK_GMAC1 107102#define R9A06G032_HCLK_GPIO0 108103#define R9A06G032_HCLK_GPIO1 109104#define R9A06G032_HCLK_GPIO2 110105#define R9A06G032_HCLK_HSR 111106#define R9A06G032_HCLK_I2C0 112107#define R9A06G032_HCLK_I2C1 113108#define R9A06G032_HCLK_LCD 114109#define R9A06G032_HCLK_MSEBI_M 115110#define R9A06G032_HCLK_MSEBI_S 116111#define R9A06G032_HCLK_NAND 117112#define R9A06G032_HCLK_PG_I 118113#define R9A06G032_HCLK_PG19 119114#define R9A06G032_HCLK_PG20 120115#define R9A06G032_HCLK_PG3 121116#define R9A06G032_HCLK_PG4 122117#define R9A06G032_HCLK_QSPI0 123118#define R9A06G032_HCLK_QSPI1 124119#define R9A06G032_HCLK_ROM 125120#define R9A06G032_HCLK_RTC 126121#define R9A06G032_HCLK_SDIO0 127122#define R9A06G032_HCLK_SDIO1 128123#define R9A06G032_HCLK_SEMAP 129124#define R9A06G032_HCLK_SPI0 130125#define R9A06G032_HCLK_SPI1 131126#define R9A06G032_HCLK_SPI2 132127#define R9A06G032_HCLK_SPI3 133128#define R9A06G032_HCLK_SPI4 134129#define R9A06G032_HCLK_SPI5 135130#define R9A06G032_HCLK_SWITCH 136131#define R9A06G032_HCLK_SWITCH_RG 137132#define R9A06G032_HCLK_UART0 138133#define R9A06G032_HCLK_UART1 139134#define R9A06G032_HCLK_UART2 140135#define R9A06G032_HCLK_UART3 141136#define R9A06G032_HCLK_UART4 142137#define R9A06G032_HCLK_UART5 143138#define R9A06G032_HCLK_UART6 144139#define R9A06G032_HCLK_UART7 145140#define R9A06G032_CLK_UART0 146141#define R9A06G032_CLK_UART1 147142#define R9A06G032_CLK_UART2 148143#define R9A06G032_CLK_UART3 149144#define R9A06G032_CLK_UART4 150145#define R9A06G032_CLK_UART5 151146#define R9A06G032_CLK_UART6 152147#define R9A06G032_CLK_UART7 153148 149#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */150