257 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 *3 * Copyright (C) 2022 Renesas Electronics Corp.4 */5#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__6#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* R9A07G043 CPG Core Clocks */11#define R9A07G043_CLK_I 012#define R9A07G043_CLK_I2 113#define R9A07G043_CLK_S0 214#define R9A07G043_CLK_SPI0 315#define R9A07G043_CLK_SPI1 416#define R9A07G043_CLK_SD0 517#define R9A07G043_CLK_SD1 618#define R9A07G043_CLK_M0 719#define R9A07G043_CLK_M2 8 /* RZ/G2UL Only */20#define R9A07G043_CLK_M3 9 /* RZ/G2UL Only */21#define R9A07G043_CLK_HP 1022#define R9A07G043_CLK_TSU 1123#define R9A07G043_CLK_ZT 1224#define R9A07G043_CLK_P0 1325#define R9A07G043_CLK_P1 1426#define R9A07G043_CLK_P2 1527#define R9A07G043_CLK_AT 16 /* RZ/G2UL Only */28#define R9A07G043_OSCCLK 1729#define R9A07G043_CLK_P0_DIV2 1830 31/* R9A07G043 Module Clocks */32#define R9A07G043_CA55_SCLK 0 /* RZ/G2UL Only */33#define R9A07G043_CA55_PCLK 1 /* RZ/G2UL Only */34#define R9A07G043_CA55_ATCLK 2 /* RZ/G2UL Only */35#define R9A07G043_CA55_GICCLK 3 /* RZ/G2UL Only */36#define R9A07G043_CA55_PERICLK 4 /* RZ/G2UL Only */37#define R9A07G043_CA55_ACLK 5 /* RZ/G2UL Only */38#define R9A07G043_CA55_TSCLK 6 /* RZ/G2UL Only */39#define R9A07G043_GIC600_GICCLK 7 /* RZ/G2UL Only */40#define R9A07G043_IA55_CLK 8 /* RZ/G2UL Only */41#define R9A07G043_IA55_PCLK 9 /* RZ/G2UL Only */42#define R9A07G043_MHU_PCLK 10 /* RZ/G2UL Only */43#define R9A07G043_SYC_CNT_CLK 1144#define R9A07G043_DMAC_ACLK 1245#define R9A07G043_DMAC_PCLK 1346#define R9A07G043_OSTM0_PCLK 1447#define R9A07G043_OSTM1_PCLK 1548#define R9A07G043_OSTM2_PCLK 1649#define R9A07G043_MTU_X_MCK_MTU3 1750#define R9A07G043_POE3_CLKM_POE 1851#define R9A07G043_WDT0_PCLK 1952#define R9A07G043_WDT0_CLK 2053#define R9A07G043_WDT2_PCLK 21 /* RZ/G2UL Only */54#define R9A07G043_WDT2_CLK 22 /* RZ/G2UL Only */55#define R9A07G043_SPI_CLK2 2356#define R9A07G043_SPI_CLK 2457#define R9A07G043_SDHI0_IMCLK 2558#define R9A07G043_SDHI0_IMCLK2 2659#define R9A07G043_SDHI0_CLK_HS 2760#define R9A07G043_SDHI0_ACLK 2861#define R9A07G043_SDHI1_IMCLK 2962#define R9A07G043_SDHI1_IMCLK2 3063#define R9A07G043_SDHI1_CLK_HS 3164#define R9A07G043_SDHI1_ACLK 3265#define R9A07G043_ISU_ACLK 33 /* RZ/G2UL Only */66#define R9A07G043_ISU_PCLK 34 /* RZ/G2UL Only */67#define R9A07G043_CRU_SYSCLK 35 /* RZ/G2UL Only */68#define R9A07G043_CRU_VCLK 36 /* RZ/G2UL Only */69#define R9A07G043_CRU_PCLK 37 /* RZ/G2UL Only */70#define R9A07G043_CRU_ACLK 38 /* RZ/G2UL Only */71#define R9A07G043_LCDC_CLK_A 39 /* RZ/G2UL Only */72#define R9A07G043_LCDC_CLK_P 40 /* RZ/G2UL Only */73#define R9A07G043_LCDC_CLK_D 41 /* RZ/G2UL Only */74#define R9A07G043_SSI0_PCLK2 4275#define R9A07G043_SSI0_PCLK_SFR 4376#define R9A07G043_SSI1_PCLK2 4477#define R9A07G043_SSI1_PCLK_SFR 4578#define R9A07G043_SSI2_PCLK2 4679#define R9A07G043_SSI2_PCLK_SFR 4780#define R9A07G043_SSI3_PCLK2 4881#define R9A07G043_SSI3_PCLK_SFR 4982#define R9A07G043_SRC_CLKP 50 /* RZ/G2UL Only */83#define R9A07G043_USB_U2H0_HCLK 5184#define R9A07G043_USB_U2H1_HCLK 5285#define R9A07G043_USB_U2P_EXR_CPUCLK 5386#define R9A07G043_USB_PCLK 5487#define R9A07G043_ETH0_CLK_AXI 5588#define R9A07G043_ETH0_CLK_CHI 5689#define R9A07G043_ETH1_CLK_AXI 5790#define R9A07G043_ETH1_CLK_CHI 5891#define R9A07G043_I2C0_PCLK 5992#define R9A07G043_I2C1_PCLK 6093#define R9A07G043_I2C2_PCLK 6194#define R9A07G043_I2C3_PCLK 6295#define R9A07G043_SCIF0_CLK_PCK 6396#define R9A07G043_SCIF1_CLK_PCK 6497#define R9A07G043_SCIF2_CLK_PCK 6598#define R9A07G043_SCIF3_CLK_PCK 6699#define R9A07G043_SCIF4_CLK_PCK 67100#define R9A07G043_SCI0_CLKP 68101#define R9A07G043_SCI1_CLKP 69102#define R9A07G043_IRDA_CLKP 70103#define R9A07G043_RSPI0_CLKB 71104#define R9A07G043_RSPI1_CLKB 72105#define R9A07G043_RSPI2_CLKB 73106#define R9A07G043_CANFD_PCLK 74107#define R9A07G043_GPIO_HCLK 75108#define R9A07G043_ADC_ADCLK 76109#define R9A07G043_ADC_PCLK 77110#define R9A07G043_TSU_PCLK 78111#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */112#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */113#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */114#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */115#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */116#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */117#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */118#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */119#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */120 121/* R9A07G043 Resets */122#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */123#define R9A07G043_CA55_RST_1_1 1 /* RZ/G2UL Only */124#define R9A07G043_CA55_RST_3_0 2 /* RZ/G2UL Only */125#define R9A07G043_CA55_RST_3_1 3 /* RZ/G2UL Only */126#define R9A07G043_CA55_RST_4 4 /* RZ/G2UL Only */127#define R9A07G043_CA55_RST_5 5 /* RZ/G2UL Only */128#define R9A07G043_CA55_RST_6 6 /* RZ/G2UL Only */129#define R9A07G043_CA55_RST_7 7 /* RZ/G2UL Only */130#define R9A07G043_CA55_RST_8 8 /* RZ/G2UL Only */131#define R9A07G043_CA55_RST_9 9 /* RZ/G2UL Only */132#define R9A07G043_CA55_RST_10 10 /* RZ/G2UL Only */133#define R9A07G043_CA55_RST_11 11 /* RZ/G2UL Only */134#define R9A07G043_CA55_RST_12 12 /* RZ/G2UL Only */135#define R9A07G043_GIC600_GICRESET_N 13 /* RZ/G2UL Only */136#define R9A07G043_GIC600_DBG_GICRESET_N 14 /* RZ/G2UL Only */137#define R9A07G043_IA55_RESETN 15 /* RZ/G2UL Only */138#define R9A07G043_MHU_RESETN 16 /* RZ/G2UL Only */139#define R9A07G043_DMAC_ARESETN 17140#define R9A07G043_DMAC_RST_ASYNC 18141#define R9A07G043_SYC_RESETN 19142#define R9A07G043_OSTM0_PRESETZ 20143#define R9A07G043_OSTM1_PRESETZ 21144#define R9A07G043_OSTM2_PRESETZ 22145#define R9A07G043_MTU_X_PRESET_MTU3 23146#define R9A07G043_POE3_RST_M_REG 24147#define R9A07G043_WDT0_PRESETN 25148#define R9A07G043_WDT2_PRESETN 26 /* RZ/G2UL Only */149#define R9A07G043_SPI_RST 27150#define R9A07G043_SDHI0_IXRST 28151#define R9A07G043_SDHI1_IXRST 29152#define R9A07G043_ISU_ARESETN 30 /* RZ/G2UL Only */153#define R9A07G043_ISU_PRESETN 31 /* RZ/G2UL Only */154#define R9A07G043_CRU_CMN_RSTB 32 /* RZ/G2UL Only */155#define R9A07G043_CRU_PRESETN 33 /* RZ/G2UL Only */156#define R9A07G043_CRU_ARESETN 34 /* RZ/G2UL Only */157#define R9A07G043_LCDC_RESET_N 35 /* RZ/G2UL Only */158#define R9A07G043_SSI0_RST_M2_REG 36159#define R9A07G043_SSI1_RST_M2_REG 37160#define R9A07G043_SSI2_RST_M2_REG 38161#define R9A07G043_SSI3_RST_M2_REG 39162#define R9A07G043_SRC_RST 40 /* RZ/G2UL Only */163#define R9A07G043_USB_U2H0_HRESETN 41164#define R9A07G043_USB_U2H1_HRESETN 42165#define R9A07G043_USB_U2P_EXL_SYSRST 43166#define R9A07G043_USB_PRESETN 44167#define R9A07G043_ETH0_RST_HW_N 45168#define R9A07G043_ETH1_RST_HW_N 46169#define R9A07G043_I2C0_MRST 47170#define R9A07G043_I2C1_MRST 48171#define R9A07G043_I2C2_MRST 49172#define R9A07G043_I2C3_MRST 50173#define R9A07G043_SCIF0_RST_SYSTEM_N 51174#define R9A07G043_SCIF1_RST_SYSTEM_N 52175#define R9A07G043_SCIF2_RST_SYSTEM_N 53176#define R9A07G043_SCIF3_RST_SYSTEM_N 54177#define R9A07G043_SCIF4_RST_SYSTEM_N 55178#define R9A07G043_SCI0_RST 56179#define R9A07G043_SCI1_RST 57180#define R9A07G043_IRDA_RST 58181#define R9A07G043_RSPI0_RST 59182#define R9A07G043_RSPI1_RST 60183#define R9A07G043_RSPI2_RST 61184#define R9A07G043_CANFD_RSTP_N 62185#define R9A07G043_CANFD_RSTC_N 63186#define R9A07G043_GPIO_RSTN 64187#define R9A07G043_GPIO_PORT_RESETN 65188#define R9A07G043_GPIO_SPARE_RESETN 66189#define R9A07G043_ADC_PRESETN 67190#define R9A07G043_ADC_ADRST_N 68191#define R9A07G043_TSU_PRESETN 69192#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */193#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */194#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */195#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */196#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */197#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */198#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */199#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */200#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */201#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */202 203/* Power domain IDs. */204#define R9A07G043_PD_ALWAYS_ON 0205#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */206#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */207#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */208#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */209#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */210#define R9A07G043_PD_DMAC 6211#define R9A07G043_PD_GTM0 7212#define R9A07G043_PD_GTM1 8213#define R9A07G043_PD_GTM2 9214#define R9A07G043_PD_MTU 10215#define R9A07G043_PD_POE3 11216#define R9A07G043_PD_WDT0 12217#define R9A07G043_PD_SPI 13218#define R9A07G043_PD_SDHI0 14219#define R9A07G043_PD_SDHI1 15220#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */221#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */222#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */223#define R9A07G043_PD_SSI0 19224#define R9A07G043_PD_SSI1 20225#define R9A07G043_PD_SSI2 21226#define R9A07G043_PD_SSI3 22227#define R9A07G043_PD_SRC 23228#define R9A07G043_PD_USB0 24229#define R9A07G043_PD_USB1 25230#define R9A07G043_PD_USB_PHY 26231#define R9A07G043_PD_ETHER0 27232#define R9A07G043_PD_ETHER1 28233#define R9A07G043_PD_I2C0 29234#define R9A07G043_PD_I2C1 30235#define R9A07G043_PD_I2C2 31236#define R9A07G043_PD_I2C3 32237#define R9A07G043_PD_SCIF0 33238#define R9A07G043_PD_SCIF1 34239#define R9A07G043_PD_SCIF2 35240#define R9A07G043_PD_SCIF3 36241#define R9A07G043_PD_SCIF4 37242#define R9A07G043_PD_SCI0 38243#define R9A07G043_PD_SCI1 39244#define R9A07G043_PD_IRDA 40245#define R9A07G043_PD_RSPI0 41246#define R9A07G043_PD_RSPI1 42247#define R9A07G043_PD_RSPI2 43248#define R9A07G043_PD_CANFD 44249#define R9A07G043_PD_ADC 45250#define R9A07G043_PD_TSU 46251#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */252#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */253#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */254#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */255 256#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */257