279 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 *3 * Copyright (C) 2021 Renesas Electronics Corp.4 */5#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__6#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* R9A07G044 CPG Core Clocks */11#define R9A07G044_CLK_I 012#define R9A07G044_CLK_I2 113#define R9A07G044_CLK_G 214#define R9A07G044_CLK_S0 315#define R9A07G044_CLK_S1 416#define R9A07G044_CLK_SPI0 517#define R9A07G044_CLK_SPI1 618#define R9A07G044_CLK_SD0 719#define R9A07G044_CLK_SD1 820#define R9A07G044_CLK_M0 921#define R9A07G044_CLK_M1 1022#define R9A07G044_CLK_M2 1123#define R9A07G044_CLK_M3 1224#define R9A07G044_CLK_M4 1325#define R9A07G044_CLK_HP 1426#define R9A07G044_CLK_TSU 1527#define R9A07G044_CLK_ZT 1628#define R9A07G044_CLK_P0 1729#define R9A07G044_CLK_P1 1830#define R9A07G044_CLK_P2 1931#define R9A07G044_CLK_AT 2032#define R9A07G044_OSCCLK 2133#define R9A07G044_CLK_P0_DIV2 2234 35/* R9A07G044 Module Clocks */36#define R9A07G044_CA55_SCLK 037#define R9A07G044_CA55_PCLK 138#define R9A07G044_CA55_ATCLK 239#define R9A07G044_CA55_GICCLK 340#define R9A07G044_CA55_PERICLK 441#define R9A07G044_CA55_ACLK 542#define R9A07G044_CA55_TSCLK 643#define R9A07G044_GIC600_GICCLK 744#define R9A07G044_IA55_CLK 845#define R9A07G044_IA55_PCLK 946#define R9A07G044_MHU_PCLK 1047#define R9A07G044_SYC_CNT_CLK 1148#define R9A07G044_DMAC_ACLK 1249#define R9A07G044_DMAC_PCLK 1350#define R9A07G044_OSTM0_PCLK 1451#define R9A07G044_OSTM1_PCLK 1552#define R9A07G044_OSTM2_PCLK 1653#define R9A07G044_MTU_X_MCK_MTU3 1754#define R9A07G044_POE3_CLKM_POE 1855#define R9A07G044_GPT_PCLK 1956#define R9A07G044_POEG_A_CLKP 2057#define R9A07G044_POEG_B_CLKP 2158#define R9A07G044_POEG_C_CLKP 2259#define R9A07G044_POEG_D_CLKP 2360#define R9A07G044_WDT0_PCLK 2461#define R9A07G044_WDT0_CLK 2562#define R9A07G044_WDT1_PCLK 2663#define R9A07G044_WDT1_CLK 2764#define R9A07G044_WDT2_PCLK 2865#define R9A07G044_WDT2_CLK 2966#define R9A07G044_SPI_CLK2 3067#define R9A07G044_SPI_CLK 3168#define R9A07G044_SDHI0_IMCLK 3269#define R9A07G044_SDHI0_IMCLK2 3370#define R9A07G044_SDHI0_CLK_HS 3471#define R9A07G044_SDHI0_ACLK 3572#define R9A07G044_SDHI1_IMCLK 3673#define R9A07G044_SDHI1_IMCLK2 3774#define R9A07G044_SDHI1_CLK_HS 3875#define R9A07G044_SDHI1_ACLK 3976#define R9A07G044_GPU_CLK 4077#define R9A07G044_GPU_AXI_CLK 4178#define R9A07G044_GPU_ACE_CLK 4279#define R9A07G044_ISU_ACLK 4380#define R9A07G044_ISU_PCLK 4481#define R9A07G044_H264_CLK_A 4582#define R9A07G044_H264_CLK_P 4683#define R9A07G044_CRU_SYSCLK 4784#define R9A07G044_CRU_VCLK 4885#define R9A07G044_CRU_PCLK 4986#define R9A07G044_CRU_ACLK 5087#define R9A07G044_MIPI_DSI_PLLCLK 5188#define R9A07G044_MIPI_DSI_SYSCLK 5289#define R9A07G044_MIPI_DSI_ACLK 5390#define R9A07G044_MIPI_DSI_PCLK 5491#define R9A07G044_MIPI_DSI_VCLK 5592#define R9A07G044_MIPI_DSI_LPCLK 5693#define R9A07G044_LCDC_CLK_A 5794#define R9A07G044_LCDC_CLK_P 5895#define R9A07G044_LCDC_CLK_D 5996#define R9A07G044_SSI0_PCLK2 6097#define R9A07G044_SSI0_PCLK_SFR 6198#define R9A07G044_SSI1_PCLK2 6299#define R9A07G044_SSI1_PCLK_SFR 63100#define R9A07G044_SSI2_PCLK2 64101#define R9A07G044_SSI2_PCLK_SFR 65102#define R9A07G044_SSI3_PCLK2 66103#define R9A07G044_SSI3_PCLK_SFR 67104#define R9A07G044_SRC_CLKP 68105#define R9A07G044_USB_U2H0_HCLK 69106#define R9A07G044_USB_U2H1_HCLK 70107#define R9A07G044_USB_U2P_EXR_CPUCLK 71108#define R9A07G044_USB_PCLK 72109#define R9A07G044_ETH0_CLK_AXI 73110#define R9A07G044_ETH0_CLK_CHI 74111#define R9A07G044_ETH1_CLK_AXI 75112#define R9A07G044_ETH1_CLK_CHI 76113#define R9A07G044_I2C0_PCLK 77114#define R9A07G044_I2C1_PCLK 78115#define R9A07G044_I2C2_PCLK 79116#define R9A07G044_I2C3_PCLK 80117#define R9A07G044_SCIF0_CLK_PCK 81118#define R9A07G044_SCIF1_CLK_PCK 82119#define R9A07G044_SCIF2_CLK_PCK 83120#define R9A07G044_SCIF3_CLK_PCK 84121#define R9A07G044_SCIF4_CLK_PCK 85122#define R9A07G044_SCI0_CLKP 86123#define R9A07G044_SCI1_CLKP 87124#define R9A07G044_IRDA_CLKP 88125#define R9A07G044_RSPI0_CLKB 89126#define R9A07G044_RSPI1_CLKB 90127#define R9A07G044_RSPI2_CLKB 91128#define R9A07G044_CANFD_PCLK 92129#define R9A07G044_GPIO_HCLK 93130#define R9A07G044_ADC_ADCLK 94131#define R9A07G044_ADC_PCLK 95132#define R9A07G044_TSU_PCLK 96133 134/* R9A07G044 Resets */135#define R9A07G044_CA55_RST_1_0 0136#define R9A07G044_CA55_RST_1_1 1137#define R9A07G044_CA55_RST_3_0 2138#define R9A07G044_CA55_RST_3_1 3139#define R9A07G044_CA55_RST_4 4140#define R9A07G044_CA55_RST_5 5141#define R9A07G044_CA55_RST_6 6142#define R9A07G044_CA55_RST_7 7143#define R9A07G044_CA55_RST_8 8144#define R9A07G044_CA55_RST_9 9145#define R9A07G044_CA55_RST_10 10146#define R9A07G044_CA55_RST_11 11147#define R9A07G044_CA55_RST_12 12148#define R9A07G044_GIC600_GICRESET_N 13149#define R9A07G044_GIC600_DBG_GICRESET_N 14150#define R9A07G044_IA55_RESETN 15151#define R9A07G044_MHU_RESETN 16152#define R9A07G044_DMAC_ARESETN 17153#define R9A07G044_DMAC_RST_ASYNC 18154#define R9A07G044_SYC_RESETN 19155#define R9A07G044_OSTM0_PRESETZ 20156#define R9A07G044_OSTM1_PRESETZ 21157#define R9A07G044_OSTM2_PRESETZ 22158#define R9A07G044_MTU_X_PRESET_MTU3 23159#define R9A07G044_POE3_RST_M_REG 24160#define R9A07G044_GPT_RST_C 25161#define R9A07G044_POEG_A_RST 26162#define R9A07G044_POEG_B_RST 27163#define R9A07G044_POEG_C_RST 28164#define R9A07G044_POEG_D_RST 29165#define R9A07G044_WDT0_PRESETN 30166#define R9A07G044_WDT1_PRESETN 31167#define R9A07G044_WDT2_PRESETN 32168#define R9A07G044_SPI_RST 33169#define R9A07G044_SDHI0_IXRST 34170#define R9A07G044_SDHI1_IXRST 35171#define R9A07G044_GPU_RESETN 36172#define R9A07G044_GPU_AXI_RESETN 37173#define R9A07G044_GPU_ACE_RESETN 38174#define R9A07G044_ISU_ARESETN 39175#define R9A07G044_ISU_PRESETN 40176#define R9A07G044_H264_X_RESET_VCP 41177#define R9A07G044_H264_CP_PRESET_P 42178#define R9A07G044_CRU_CMN_RSTB 43179#define R9A07G044_CRU_PRESETN 44180#define R9A07G044_CRU_ARESETN 45181#define R9A07G044_MIPI_DSI_CMN_RSTB 46182#define R9A07G044_MIPI_DSI_ARESET_N 47183#define R9A07G044_MIPI_DSI_PRESET_N 48184#define R9A07G044_LCDC_RESET_N 49185#define R9A07G044_SSI0_RST_M2_REG 50186#define R9A07G044_SSI1_RST_M2_REG 51187#define R9A07G044_SSI2_RST_M2_REG 52188#define R9A07G044_SSI3_RST_M2_REG 53189#define R9A07G044_SRC_RST 54190#define R9A07G044_USB_U2H0_HRESETN 55191#define R9A07G044_USB_U2H1_HRESETN 56192#define R9A07G044_USB_U2P_EXL_SYSRST 57193#define R9A07G044_USB_PRESETN 58194#define R9A07G044_ETH0_RST_HW_N 59195#define R9A07G044_ETH1_RST_HW_N 60196#define R9A07G044_I2C0_MRST 61197#define R9A07G044_I2C1_MRST 62198#define R9A07G044_I2C2_MRST 63199#define R9A07G044_I2C3_MRST 64200#define R9A07G044_SCIF0_RST_SYSTEM_N 65201#define R9A07G044_SCIF1_RST_SYSTEM_N 66202#define R9A07G044_SCIF2_RST_SYSTEM_N 67203#define R9A07G044_SCIF3_RST_SYSTEM_N 68204#define R9A07G044_SCIF4_RST_SYSTEM_N 69205#define R9A07G044_SCI0_RST 70206#define R9A07G044_SCI1_RST 71207#define R9A07G044_IRDA_RST 72208#define R9A07G044_RSPI0_RST 73209#define R9A07G044_RSPI1_RST 74210#define R9A07G044_RSPI2_RST 75211#define R9A07G044_CANFD_RSTP_N 76212#define R9A07G044_CANFD_RSTC_N 77213#define R9A07G044_GPIO_RSTN 78214#define R9A07G044_GPIO_PORT_RESETN 79215#define R9A07G044_GPIO_SPARE_RESETN 80216#define R9A07G044_ADC_PRESETN 81217#define R9A07G044_ADC_ADRST_N 82218#define R9A07G044_TSU_PRESETN 83219 220/* Power domain IDs. */221#define R9A07G044_PD_ALWAYS_ON 0222#define R9A07G044_PD_GIC 1223#define R9A07G044_PD_IA55 2224#define R9A07G044_PD_MHU 3225#define R9A07G044_PD_CORESIGHT 4226#define R9A07G044_PD_SYC 5227#define R9A07G044_PD_DMAC 6228#define R9A07G044_PD_GTM0 7229#define R9A07G044_PD_GTM1 8230#define R9A07G044_PD_GTM2 9231#define R9A07G044_PD_MTU 10232#define R9A07G044_PD_POE3 11233#define R9A07G044_PD_GPT 12234#define R9A07G044_PD_POEGA 13235#define R9A07G044_PD_POEGB 14236#define R9A07G044_PD_POEGC 15237#define R9A07G044_PD_POEGD 16238#define R9A07G044_PD_WDT0 17239#define R9A07G044_PD_WDT1 18240#define R9A07G044_PD_SPI 19241#define R9A07G044_PD_SDHI0 20242#define R9A07G044_PD_SDHI1 21243#define R9A07G044_PD_3DGE 22244#define R9A07G044_PD_ISU 23245#define R9A07G044_PD_VCPL4 24246#define R9A07G044_PD_CRU 25247#define R9A07G044_PD_MIPI_DSI 26248#define R9A07G044_PD_LCDC 27249#define R9A07G044_PD_SSI0 28250#define R9A07G044_PD_SSI1 29251#define R9A07G044_PD_SSI2 30252#define R9A07G044_PD_SSI3 31253#define R9A07G044_PD_SRC 32254#define R9A07G044_PD_USB0 33255#define R9A07G044_PD_USB1 34256#define R9A07G044_PD_USB_PHY 35257#define R9A07G044_PD_ETHER0 36258#define R9A07G044_PD_ETHER1 37259#define R9A07G044_PD_I2C0 38260#define R9A07G044_PD_I2C1 39261#define R9A07G044_PD_I2C2 40262#define R9A07G044_PD_I2C3 41263#define R9A07G044_PD_SCIF0 42264#define R9A07G044_PD_SCIF1 43265#define R9A07G044_PD_SCIF2 44266#define R9A07G044_PD_SCIF3 45267#define R9A07G044_PD_SCIF4 46268#define R9A07G044_PD_SCI0 47269#define R9A07G044_PD_SCI1 48270#define R9A07G044_PD_IRDA 49271#define R9A07G044_PD_RSPI0 50272#define R9A07G044_PD_RSPI1 51273#define R9A07G044_PD_RSPI2 52274#define R9A07G044_PD_CANFD 53275#define R9A07G044_PD_ADC 54276#define R9A07G044_PD_TSU 55277 278#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */279