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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 *3 * Copyright (C) 2024 Renesas Electronics Corp.4 */5#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__6#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__7 8#include <dt-bindings/clock/renesas-cpg-mssr.h>9 10/* Core Clock list */11#define R9A09G057_SYS_0_PCLK 012#define R9A09G057_CA55_0_CORE_CLK0 113#define R9A09G057_CA55_0_CORE_CLK1 214#define R9A09G057_CA55_0_CORE_CLK2 315#define R9A09G057_CA55_0_CORE_CLK3 416#define R9A09G057_CA55_0_PERIPHCLK 517#define R9A09G057_CM33_CLK0 618#define R9A09G057_CST_0_SWCLKTCK 719#define R9A09G057_IOTOP_0_SHCLK 820 21#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */22