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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.4 * Author: Xing Zheng <zhengxing@rock-chips.com>5 */6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H9 10/* core clocks */11#define PLL_APLL 112#define PLL_DPLL 213#define PLL_GPLL 314#define ARMCLK 415 16/* sclk gates (special clocks) */17#define SCLK_GPU 6418#define SCLK_SPI 6519#define SCLK_SDMMC 6820#define SCLK_SDIO 6921#define SCLK_EMMC 7122#define SCLK_NANDC 7623#define SCLK_UART0 7724#define SCLK_UART1 7825#define SCLK_UART2 7926#define SCLK_I2S 8227#define SCLK_SPDIF 8328#define SCLK_TIMER0 8529#define SCLK_TIMER1 8630#define SCLK_TIMER2 8731#define SCLK_TIMER3 8832#define SCLK_OTGPHY0 9333#define SCLK_LCDC 10034#define SCLK_HDMI 10935#define SCLK_HEVC 11136#define SCLK_I2S_OUT 11337#define SCLK_SDMMC_DRV 11438#define SCLK_SDIO_DRV 11539#define SCLK_EMMC_DRV 11740#define SCLK_SDMMC_SAMPLE 11841#define SCLK_SDIO_SAMPLE 11942#define SCLK_EMMC_SAMPLE 12143#define SCLK_PVTM_CORE 12344#define SCLK_PVTM_GPU 12445#define SCLK_PVTM_VIDEO 12546#define SCLK_MAC 15147#define SCLK_MACREF 15248#define SCLK_MACPLL 15349#define SCLK_SFC 16050 51/* aclk gates */52#define ACLK_DMAC2 19453#define ACLK_LCDC 19754#define ACLK_VIO 20355#define ACLK_VCODEC 20856#define ACLK_CPU 20957#define ACLK_PERI 21058 59/* pclk gates */60#define PCLK_GPIO0 32061#define PCLK_GPIO1 32162#define PCLK_GPIO2 32263#define PCLK_GRF 32964#define PCLK_I2C0 33265#define PCLK_I2C1 33366#define PCLK_I2C2 33467#define PCLK_SPI 33868#define PCLK_UART0 34169#define PCLK_UART1 34270#define PCLK_UART2 34371#define PCLK_PWM 35072#define PCLK_TIMER 35373#define PCLK_HDMI 36074#define PCLK_CPU 36275#define PCLK_PERI 36376#define PCLK_DDRUPCTL 36477#define PCLK_WDT 36878#define PCLK_ACODEC 36979 80/* hclk gates */81#define HCLK_OTG0 44982#define HCLK_OTG1 45083#define HCLK_NANDC 45384#define HCLK_SFC 45485#define HCLK_SDMMC 45686#define HCLK_SDIO 45787#define HCLK_EMMC 45988#define HCLK_MAC 46089#define HCLK_I2S 46290#define HCLK_LCDC 46591#define HCLK_ROM 46792#define HCLK_VIO_BUS 47293#define HCLK_VCODEC 47694#define HCLK_CPU 47795#define HCLK_PERI 47896 97/* soft-reset indices */98#define SRST_CORE0 099#define SRST_CORE1 1100#define SRST_CORE0_DBG 4101#define SRST_CORE1_DBG 5102#define SRST_CORE0_POR 8103#define SRST_CORE1_POR 9104#define SRST_L2C 12105#define SRST_TOPDBG 13106#define SRST_STRC_SYS_A 14107#define SRST_PD_CORE_NIU 15108 109#define SRST_TIMER2 16110#define SRST_CPUSYS_H 17111#define SRST_AHB2APB_H 19112#define SRST_TIMER3 20113#define SRST_INTMEM 21114#define SRST_ROM 22115#define SRST_PERI_NIU 23116#define SRST_I2S 24117#define SRST_DDR_PLL 25118#define SRST_GPU_DLL 26119#define SRST_TIMER0 27120#define SRST_TIMER1 28121#define SRST_CORE_DLL 29122#define SRST_EFUSE_P 30123#define SRST_ACODEC_P 31124 125#define SRST_GPIO0 32126#define SRST_GPIO1 33127#define SRST_GPIO2 34128#define SRST_UART0 39129#define SRST_UART1 40130#define SRST_UART2 41131#define SRST_I2C0 43132#define SRST_I2C1 44133#define SRST_I2C2 45134#define SRST_SFC 47135 136#define SRST_PWM0 48137#define SRST_DAP 51138#define SRST_DAP_SYS 52139#define SRST_GRF 55140#define SRST_PERIPHSYS_A 57141#define SRST_PERIPHSYS_H 58142#define SRST_PERIPHSYS_P 59143#define SRST_CPU_PERI 61144#define SRST_EMEM_PERI 62145#define SRST_USB_PERI 63146 147#define SRST_DMA2 64148#define SRST_MAC 66149#define SRST_NANDC 68150#define SRST_USBOTG0 69151#define SRST_OTGC0 71152#define SRST_USBOTG1 72153#define SRST_OTGC1 74154#define SRST_DDRMSCH 79155 156#define SRST_MMC0 81157#define SRST_SDIO 82158#define SRST_EMMC 83159#define SRST_SPI0 84160#define SRST_WDT 86161#define SRST_DDRPHY 88162#define SRST_DDRPHY_P 89163#define SRST_DDRCTRL 90164#define SRST_DDRCTRL_P 91165 166#define SRST_HDMI_P 96167#define SRST_VIO_BUS_H 99168#define SRST_UTMI0 103169#define SRST_UTMI1 104170#define SRST_USBPOR 105171 172#define SRST_VCODEC_A 112173#define SRST_VCODEC_H 113174#define SRST_VIO1_A 114175#define SRST_HEVC 115176#define SRST_VCODEC_NIU_A 116177#define SRST_LCDC1_A 117178#define SRST_LCDC1_H 118179#define SRST_LCDC1_D 119180#define SRST_GPU 120181#define SRST_GPU_NIU_A 122182 183#define SRST_DBG_P 131184 185#endif186