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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.4 * Author: Elaine <zhangqing@rock-chips.com>5 */6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H9 10/* core clocks */11#define PLL_APLL 112#define PLL_DPLL 213#define PLL_CPLL 314#define PLL_GPLL 415#define ARMCLK 516#define PLL_GPLL_DIV2 617#define PLL_GPLL_DIV3 718 19/* sclk gates (special clocks) */20#define SCLK_SPI0 6521#define SCLK_NANDC 6722#define SCLK_SDMMC 6823#define SCLK_SDIO 6924#define SCLK_EMMC 7125#define SCLK_UART0 7726#define SCLK_UART1 7827#define SCLK_UART2 7928#define SCLK_I2S0 8029#define SCLK_I2S1 8130#define SCLK_SPDIF 8331#define SCLK_TIMER0 8532#define SCLK_TIMER1 8633#define SCLK_TIMER2 8734#define SCLK_TIMER3 8835#define SCLK_TIMER4 8936#define SCLK_TIMER5 9037#define SCLK_SARADC 9138#define SCLK_I2S_OUT 11339#define SCLK_SDMMC_DRV 11440#define SCLK_SDIO_DRV 11541#define SCLK_EMMC_DRV 11742#define SCLK_SDMMC_SAMPLE 11843#define SCLK_SDIO_SAMPLE 11944#define SCLK_EMMC_SAMPLE 12145#define SCLK_VOP 12246#define SCLK_MAC_SRC 12447#define SCLK_MAC 12648#define SCLK_MAC_REFOUT 12749#define SCLK_MAC_REF 12850#define SCLK_MAC_RX 12951#define SCLK_MAC_TX 13052#define SCLK_HEVC_CORE 13453#define SCLK_RGA 13554#define SCLK_CRYPTO 13855#define SCLK_TSP 13956#define SCLK_OTGPHY0 14257#define SCLK_OTGPHY1 14358#define SCLK_DDRC 14459#define SCLK_PVTM_FUNC 14560#define SCLK_PVTM_CORE 14661#define SCLK_PVTM_GPU 14762#define SCLK_MIPI_24M 14863#define SCLK_PVTM 14964#define SCLK_CIF_SRC 15065#define SCLK_CIF_OUT_SRC 15166#define SCLK_CIF_OUT 15267#define SCLK_SFC 15368#define SCLK_USB480M 15469 70/* dclk gates */71#define DCLK_VOP 19072#define DCLK_EBC 19173 74/* aclk gates */75#define ACLK_VIO0 19276#define ACLK_VIO1 19377#define ACLK_DMAC 19478#define ACLK_CPU 19579#define ACLK_VEPU 19680#define ACLK_VDPU 19781#define ACLK_CIF 19882#define ACLK_IEP 19983#define ACLK_LCDC0 20484#define ACLK_RGA 20585#define ACLK_PERI 21086#define ACLK_VOP 21187#define ACLK_GMAC 21288#define ACLK_GPU 21389 90/* pclk gates */91#define PCLK_SARADC 31892#define PCLK_WDT 31993#define PCLK_GPIO0 32094#define PCLK_GPIO1 32195#define PCLK_GPIO2 32296#define PCLK_GPIO3 32397#define PCLK_VIO_H2P 32498#define PCLK_MIPI 32599#define PCLK_EFUSE 326100#define PCLK_HDMI 327101#define PCLK_ACODEC 328102#define PCLK_GRF 329103#define PCLK_I2C0 332104#define PCLK_I2C1 333105#define PCLK_I2C2 334106#define PCLK_I2C3 335107#define PCLK_SPI0 338108#define PCLK_UART0 341109#define PCLK_UART1 342110#define PCLK_UART2 343111#define PCLK_TSADC 344112#define PCLK_PWM 350113#define PCLK_TIMER 353114#define PCLK_CPU 354115#define PCLK_PERI 363116#define PCLK_GMAC 367117#define PCLK_PMU_PRE 368118#define PCLK_SIM_CARD 369119#define PCLK_MIPIPHY 370120 121/* hclk gates */122#define HCLK_SPDIF 440123#define HCLK_GPS 441124#define HCLK_USBHOST 442125#define HCLK_I2S_8CH 443126#define HCLK_I2S_2CH 444127#define HCLK_VOP 452128#define HCLK_NANDC 453129#define HCLK_SDMMC 456130#define HCLK_SDIO 457131#define HCLK_EMMC 459132#define HCLK_CPU 460133#define HCLK_VEPU 461134#define HCLK_VDPU 462135#define HCLK_LCDC0 463136#define HCLK_EBC 465137#define HCLK_VIO 466138#define HCLK_RGA 467139#define HCLK_IEP 468140#define HCLK_VIO_H2P 469141#define HCLK_CIF 470142#define HCLK_HOST2 473143#define HCLK_OTG 474144#define HCLK_TSP 475145#define HCLK_CRYPTO 476146#define HCLK_PERI 478147#define HCLK_SFC 479148 149/* soft-reset indices */150#define SRST_CORE0_PO 0151#define SRST_CORE1_PO 1152#define SRST_CORE2_PO 2153#define SRST_CORE3_PO 3154#define SRST_CORE0 4155#define SRST_CORE1 5156#define SRST_CORE2 6157#define SRST_CORE3 7158#define SRST_CORE0_DBG 8159#define SRST_CORE1_DBG 9160#define SRST_CORE2_DBG 10161#define SRST_CORE3_DBG 11162#define SRST_TOPDBG 12163#define SRST_ACLK_CORE 13164#define SRST_STRC_SYS_A 14165#define SRST_L2C 15166 167#define SRST_CPUSYS_H 18168#define SRST_AHB2APBSYS_H 19169#define SRST_SPDIF 20170#define SRST_INTMEM 21171#define SRST_ROM 22172#define SRST_PERI_NIU 23173#define SRST_I2S_2CH 24174#define SRST_I2S_8CH 25175#define SRST_GPU_PVTM 26176#define SRST_FUNC_PVTM 27177#define SRST_CORE_PVTM 29178#define SRST_EFUSE_P 30179#define SRST_ACODEC_P 31180 181#define SRST_GPIO0 32182#define SRST_GPIO1 33183#define SRST_GPIO2 34184#define SRST_GPIO3 35185#define SRST_MIPIPHY_P 36186#define SRST_UART0 39187#define SRST_UART1 40188#define SRST_UART2 41189#define SRST_I2C0 43190#define SRST_I2C1 44191#define SRST_I2C2 45192#define SRST_I2C3 46193#define SRST_SFC 47194 195#define SRST_PWM 48196#define SRST_DAP_PO 50197#define SRST_DAP 51198#define SRST_DAP_SYS 52199#define SRST_CRYPTO 53200#define SRST_GRF 55201#define SRST_GMAC 56202#define SRST_PERIPH_SYS_A 57203#define SRST_PERIPH_SYS_H 58204#define SRST_PERIPH_SYS_P 59205#define SRST_SMART_CARD 60206#define SRST_CPU_PERI 61207#define SRST_EMEM_PERI 62208#define SRST_USB_PERI 63209 210#define SRST_DMA 64211#define SRST_GPS 67212#define SRST_NANDC 68213#define SRST_USBOTG0 69214#define SRST_OTGC0 71215#define SRST_USBOTG1 72216#define SRST_OTGC1 74217#define SRST_DDRMSCH 79218 219#define SRST_SDMMC 81220#define SRST_SDIO 82221#define SRST_EMMC 83222#define SRST_SPI 84223#define SRST_WDT 86224#define SRST_SARADC 87225#define SRST_DDRPHY 88226#define SRST_DDRPHY_P 89227#define SRST_DDRCTRL 90228#define SRST_DDRCTRL_P 91229#define SRST_TSP 92230#define SRST_TSP_CLKIN 93231#define SRST_HOST0_ECHI 94232 233#define SRST_HDMI_P 96234#define SRST_VIO_ARBI_H 97235#define SRST_VIO0_A 98236#define SRST_VIO_BUS_H 99237#define SRST_VOP_A 100238#define SRST_VOP_H 101239#define SRST_VOP_D 102240#define SRST_UTMI0 103241#define SRST_UTMI1 104242#define SRST_USBPOR 105243#define SRST_IEP_A 106244#define SRST_IEP_H 107245#define SRST_RGA_A 108246#define SRST_RGA_H 109247#define SRST_CIF0 110248#define SRST_PMU 111249 250#define SRST_VCODEC_A 112251#define SRST_VCODEC_H 113252#define SRST_VIO1_A 114253#define SRST_HEVC_CORE 115254#define SRST_VCODEC_NIU_A 116255#define SRST_PMU_NIU_P 117256#define SRST_LCDC0_S 119257#define SRST_GPU 120258#define SRST_GPU_NIU_A 122259#define SRST_EBC_A 123260#define SRST_EBC_H 124261 262#define SRST_CORE_DBG 128263#define SRST_DBG_P 129264#define SRST_TIMER0 130265#define SRST_TIMER1 131266#define SRST_TIMER2 132267#define SRST_TIMER3 133268#define SRST_TIMER4 134269#define SRST_TIMER5 135270#define SRST_VIO_H2P 136271#define SRST_VIO_MIPI_DSI 137272 273#endif274