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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2014 MundoReader S.L.4 * Author: Heiko Stuebner <heiko@sntech.de>5 */6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H9 10/* core clocks from */11#define PLL_APLL 112#define PLL_DPLL 213#define PLL_CPLL 314#define PLL_GPLL 415#define CORE_PERI 516#define CORE_L2C 617#define ARMCLK 718 19/* sclk gates (special clocks) */20#define SCLK_UART0 6421#define SCLK_UART1 6522#define SCLK_UART2 6623#define SCLK_UART3 6724#define SCLK_MAC 6825#define SCLK_SPI0 6926#define SCLK_SPI1 7027#define SCLK_SARADC 7128#define SCLK_SDMMC 7229#define SCLK_SDIO 7330#define SCLK_EMMC 7431#define SCLK_I2S0 7532#define SCLK_I2S1 7633#define SCLK_I2S2 7734#define SCLK_SPDIF 7835#define SCLK_CIF0 7936#define SCLK_CIF1 8037#define SCLK_OTGPHY0 8138#define SCLK_OTGPHY1 8239#define SCLK_HSADC 8340#define SCLK_TIMER0 8441#define SCLK_TIMER1 8542#define SCLK_TIMER2 8643#define SCLK_TIMER3 8744#define SCLK_TIMER4 8845#define SCLK_TIMER5 8946#define SCLK_TIMER6 9047#define SCLK_JTAG 9148#define SCLK_SMC 9249#define SCLK_TSADC 9350 51#define DCLK_LCDC0 19052#define DCLK_LCDC1 19153 54/* aclk gates */55#define ACLK_DMA1 19256#define ACLK_DMA2 19357#define ACLK_GPS 19458#define ACLK_LCDC0 19559#define ACLK_LCDC1 19660#define ACLK_GPU 19761#define ACLK_SMC 19862#define ACLK_CIF1 19963#define ACLK_IPP 20064#define ACLK_RGA 20165#define ACLK_CIF0 20266#define ACLK_CPU 20367#define ACLK_PERI 20468#define ACLK_VEPU 20569#define ACLK_VDPU 20670 71/* pclk gates */72#define PCLK_GRF 32073#define PCLK_PMU 32174#define PCLK_TIMER0 32275#define PCLK_TIMER1 32376#define PCLK_TIMER2 32477#define PCLK_TIMER3 32578#define PCLK_PWM01 32679#define PCLK_PWM23 32780#define PCLK_SPI0 32881#define PCLK_SPI1 32982#define PCLK_SARADC 33083#define PCLK_WDT 33184#define PCLK_UART0 33285#define PCLK_UART1 33386#define PCLK_UART2 33487#define PCLK_UART3 33588#define PCLK_I2C0 33689#define PCLK_I2C1 33790#define PCLK_I2C2 33891#define PCLK_I2C3 33992#define PCLK_I2C4 34093#define PCLK_GPIO0 34194#define PCLK_GPIO1 34295#define PCLK_GPIO2 34396#define PCLK_GPIO3 34497#define PCLK_GPIO4 34598#define PCLK_GPIO6 34699#define PCLK_EFUSE 347100#define PCLK_TZPC 348101#define PCLK_TSADC 349102#define PCLK_CPU 350103#define PCLK_PERI 351104#define PCLK_DDRUPCTL 352105#define PCLK_PUBL 353106 107/* hclk gates */108#define HCLK_SDMMC 448109#define HCLK_SDIO 449110#define HCLK_EMMC 450111#define HCLK_OTG0 451112#define HCLK_EMAC 452113#define HCLK_SPDIF 453114#define HCLK_I2S0 454115#define HCLK_I2S1 455116#define HCLK_I2S2 456117#define HCLK_OTG1 457118#define HCLK_HSIC 458119#define HCLK_HSADC 459120#define HCLK_PIDF 460121#define HCLK_LCDC0 461122#define HCLK_LCDC1 462123#define HCLK_ROM 463124#define HCLK_CIF0 464125#define HCLK_IPP 465126#define HCLK_RGA 466127#define HCLK_NANDC0 467128#define HCLK_CPU 468129#define HCLK_PERI 469130#define HCLK_CIF1 470131#define HCLK_VEPU 471132#define HCLK_VDPU 472133#define HCLK_HDMI 473134 135/* soft-reset indices */136#define SRST_MCORE 2137#define SRST_CORE0 3138#define SRST_CORE1 4139#define SRST_MCORE_DBG 7140#define SRST_CORE0_DBG 8141#define SRST_CORE1_DBG 9142#define SRST_CORE0_WDT 12143#define SRST_CORE1_WDT 13144#define SRST_STRC_SYS 14145#define SRST_L2C 15146 147#define SRST_CPU_AHB 17148#define SRST_AHB2APB 19149#define SRST_DMA1 20150#define SRST_INTMEM 21151#define SRST_ROM 22152#define SRST_SPDIF 26153#define SRST_TIMER0 27154#define SRST_TIMER1 28155#define SRST_EFUSE 30156 157#define SRST_GPIO0 32158#define SRST_GPIO1 33159#define SRST_GPIO2 34160#define SRST_GPIO3 35161 162#define SRST_UART0 39163#define SRST_UART1 40164#define SRST_UART2 41165#define SRST_UART3 42166#define SRST_I2C0 43167#define SRST_I2C1 44168#define SRST_I2C2 45169#define SRST_I2C3 46170#define SRST_I2C4 47171 172#define SRST_PWM0 48173#define SRST_PWM1 49174#define SRST_DAP_PO 50175#define SRST_DAP 51176#define SRST_DAP_SYS 52177#define SRST_TPIU_ATB 53178#define SRST_PMU_APB 54179#define SRST_GRF 55180#define SRST_PMU 56181#define SRST_PERI_AXI 57182#define SRST_PERI_AHB 58183#define SRST_PERI_APB 59184#define SRST_PERI_NIU 60185#define SRST_CPU_PERI 61186#define SRST_EMEM_PERI 62187#define SRST_USB_PERI 63188 189#define SRST_DMA2 64190#define SRST_SMC 65191#define SRST_MAC 66192#define SRST_NANC0 68193#define SRST_USBOTG0 69194#define SRST_USBPHY0 70195#define SRST_OTGC0 71196#define SRST_USBOTG1 72197#define SRST_USBPHY1 73198#define SRST_OTGC1 74199#define SRST_HSADC 76200#define SRST_PIDFILTER 77201#define SRST_DDR_MSCH 79202 203#define SRST_TZPC 80204#define SRST_SDMMC 81205#define SRST_SDIO 82206#define SRST_EMMC 83207#define SRST_SPI0 84208#define SRST_SPI1 85209#define SRST_WDT 86210#define SRST_SARADC 87211#define SRST_DDRPHY 88212#define SRST_DDRPHY_APB 89213#define SRST_DDRCTL 90214#define SRST_DDRCTL_APB 91215#define SRST_DDRPUB 93216 217#define SRST_VIO0_AXI 98218#define SRST_VIO0_AHB 99219#define SRST_LCDC0_AXI 100220#define SRST_LCDC0_AHB 101221#define SRST_LCDC0_DCLK 102222#define SRST_LCDC1_AXI 103223#define SRST_LCDC1_AHB 104224#define SRST_LCDC1_DCLK 105225#define SRST_IPP_AXI 106226#define SRST_IPP_AHB 107227#define SRST_RGA_AXI 108228#define SRST_RGA_AHB 109229#define SRST_CIF0 110230 231#define SRST_VCODEC_AXI 112232#define SRST_VCODEC_AHB 113233#define SRST_VIO1_AXI 114234#define SRST_VCODEC_CPU 115235#define SRST_VCODEC_NIU 116236#define SRST_GPU 120237#define SRST_GPU_NIU 122238#define SRST_TFUN_ATB 125239#define SRST_TFUN_APB 126240#define SRST_CTI4_APB 127241 242#define SRST_TPIU_APB 128243#define SRST_TRACE 129244#define SRST_CORE_DBG 130245#define SRST_DBG_APB 131246#define SRST_CTI0 132247#define SRST_CTI0_APB 133248#define SRST_CTI1 134249#define SRST_CTI1_APB 135250#define SRST_PTM_CORE0 136251#define SRST_PTM_CORE1 137252#define SRST_PTM0 138253#define SRST_PTM0_ATB 139254#define SRST_PTM1 140255#define SRST_PTM1_ATB 141256#define SRST_CTM 142257#define SRST_TS 143258 259#endif260