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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.4 * Author: Jeffy Chen <jeffy.chen@rock-chips.com>5 */6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H9 10/* core clocks */11#define PLL_APLL 112#define PLL_DPLL 213#define PLL_CPLL 314#define PLL_GPLL 415#define ARMCLK 516 17/* sclk gates (special clocks) */18#define SCLK_SPI0 6519#define SCLK_NANDC 6720#define SCLK_SDMMC 6821#define SCLK_SDIO 6922#define SCLK_EMMC 7123#define SCLK_TSADC 7224#define SCLK_UART0 7725#define SCLK_UART1 7826#define SCLK_UART2 7927#define SCLK_I2S0 8028#define SCLK_I2S1 8129#define SCLK_I2S2 8230#define SCLK_SPDIF 8331#define SCLK_TIMER0 8532#define SCLK_TIMER1 8633#define SCLK_TIMER2 8734#define SCLK_TIMER3 8835#define SCLK_TIMER4 8936#define SCLK_TIMER5 9037#define SCLK_I2S_OUT 11338#define SCLK_SDMMC_DRV 11439#define SCLK_SDIO_DRV 11540#define SCLK_EMMC_DRV 11741#define SCLK_SDMMC_SAMPLE 11842#define SCLK_SDIO_SAMPLE 11943#define SCLK_SDIO_SRC 12044#define SCLK_EMMC_SAMPLE 12145#define SCLK_VOP 12246#define SCLK_HDMI_HDCP 12347#define SCLK_MAC_SRC 12448#define SCLK_MAC_EXTCLK 12549#define SCLK_MAC 12650#define SCLK_MAC_REFOUT 12751#define SCLK_MAC_REF 12852#define SCLK_MAC_RX 12953#define SCLK_MAC_TX 13054#define SCLK_MAC_PHY 13155#define SCLK_MAC_OUT 13256#define SCLK_VDEC_CABAC 13357#define SCLK_VDEC_CORE 13458#define SCLK_RGA 13559#define SCLK_HDCP 13660#define SCLK_HDMI_CEC 13761#define SCLK_CRYPTO 13862#define SCLK_TSP 13963#define SCLK_HSADC 14064#define SCLK_WIFI 14165#define SCLK_OTGPHY0 14266#define SCLK_OTGPHY1 14367#define SCLK_HDMI_PHY 14468 69/* dclk gates */70#define DCLK_VOP 19071#define DCLK_HDMI_PHY 19172 73/* aclk gates */74#define ACLK_DMAC 19475#define ACLK_CPU 19576#define ACLK_VPU_PRE 19677#define ACLK_RKVDEC_PRE 19778#define ACLK_RGA_PRE 19879#define ACLK_IEP_PRE 19980#define ACLK_HDCP_PRE 20081#define ACLK_VOP_PRE 20182#define ACLK_VPU 20283#define ACLK_RKVDEC 20384#define ACLK_IEP 20485#define ACLK_RGA 20586#define ACLK_HDCP 20687#define ACLK_PERI 21088#define ACLK_VOP 21189#define ACLK_GMAC 21290#define ACLK_GPU 21391 92/* pclk gates */93#define PCLK_GPIO0 32094#define PCLK_GPIO1 32195#define PCLK_GPIO2 32296#define PCLK_GPIO3 32397#define PCLK_VIO_H2P 32498#define PCLK_HDCP 32599#define PCLK_EFUSE_1024 326100#define PCLK_EFUSE_256 327101#define PCLK_GRF 329102#define PCLK_I2C0 332103#define PCLK_I2C1 333104#define PCLK_I2C2 334105#define PCLK_I2C3 335106#define PCLK_SPI0 338107#define PCLK_UART0 341108#define PCLK_UART1 342109#define PCLK_UART2 343110#define PCLK_TSADC 344111#define PCLK_PWM 350112#define PCLK_TIMER 353113#define PCLK_CPU 354114#define PCLK_PERI 363115#define PCLK_HDMI_CTRL 364116#define PCLK_HDMI_PHY 365117#define PCLK_GMAC 367118 119/* hclk gates */120#define HCLK_I2S0_8CH 442121#define HCLK_I2S1_8CH 443122#define HCLK_I2S2_2CH 444123#define HCLK_SPDIF_8CH 445124#define HCLK_VOP 452125#define HCLK_NANDC 453126#define HCLK_SDMMC 456127#define HCLK_SDIO 457128#define HCLK_EMMC 459129#define HCLK_CPU 460130#define HCLK_VPU_PRE 461131#define HCLK_RKVDEC_PRE 462132#define HCLK_VIO_PRE 463133#define HCLK_VPU 464134#define HCLK_RKVDEC 465135#define HCLK_VIO 466136#define HCLK_RGA 467137#define HCLK_IEP 468138#define HCLK_VIO_H2P 469139#define HCLK_HDCP_MMU 470140#define HCLK_HOST0 471141#define HCLK_HOST1 472142#define HCLK_HOST2 473143#define HCLK_OTG 474144#define HCLK_TSP 475145#define HCLK_M_CRYPTO 476146#define HCLK_S_CRYPTO 477147#define HCLK_PERI 478148 149/* soft-reset indices */150#define SRST_CORE0_PO 0151#define SRST_CORE1_PO 1152#define SRST_CORE2_PO 2153#define SRST_CORE3_PO 3154#define SRST_CORE0 4155#define SRST_CORE1 5156#define SRST_CORE2 6157#define SRST_CORE3 7158#define SRST_CORE0_DBG 8159#define SRST_CORE1_DBG 9160#define SRST_CORE2_DBG 10161#define SRST_CORE3_DBG 11162#define SRST_TOPDBG 12163#define SRST_ACLK_CORE 13164#define SRST_NOC 14165#define SRST_L2C 15166 167#define SRST_CPUSYS_H 18168#define SRST_BUSSYS_H 19169#define SRST_SPDIF 20170#define SRST_INTMEM 21171#define SRST_ROM 22172#define SRST_OTG_ADP 23173#define SRST_I2S0 24174#define SRST_I2S1 25175#define SRST_I2S2 26176#define SRST_ACODEC_P 27177#define SRST_DFIMON 28178#define SRST_MSCH 29179#define SRST_EFUSE1024 30180#define SRST_EFUSE256 31181 182#define SRST_GPIO0 32183#define SRST_GPIO1 33184#define SRST_GPIO2 34185#define SRST_GPIO3 35186#define SRST_PERIPH_NOC_A 36187#define SRST_PERIPH_NOC_BUS_H 37188#define SRST_PERIPH_NOC_P 38189#define SRST_UART0 39190#define SRST_UART1 40191#define SRST_UART2 41192#define SRST_PHYNOC 42193#define SRST_I2C0 43194#define SRST_I2C1 44195#define SRST_I2C2 45196#define SRST_I2C3 46197 198#define SRST_PWM 48199#define SRST_A53_GIC 49200#define SRST_DAP 51201#define SRST_DAP_NOC 52202#define SRST_CRYPTO 53203#define SRST_SGRF 54204#define SRST_GRF 55205#define SRST_GMAC 56206#define SRST_PERIPH_NOC_H 58207#define SRST_MACPHY 63208 209#define SRST_DMA 64210#define SRST_NANDC 68211#define SRST_USBOTG 69212#define SRST_OTGC 70213#define SRST_USBHOST0 71214#define SRST_HOST_CTRL0 72215#define SRST_USBHOST1 73216#define SRST_HOST_CTRL1 74217#define SRST_USBHOST2 75218#define SRST_HOST_CTRL2 76219#define SRST_USBPOR0 77220#define SRST_USBPOR1 78221#define SRST_DDRMSCH 79222 223#define SRST_SMART_CARD 80224#define SRST_SDMMC 81225#define SRST_SDIO 82226#define SRST_EMMC 83227#define SRST_SPI 84228#define SRST_TSP_H 85229#define SRST_TSP 86230#define SRST_TSADC 87231#define SRST_DDRPHY 88232#define SRST_DDRPHY_P 89233#define SRST_DDRCTRL 90234#define SRST_DDRCTRL_P 91235#define SRST_HOST0_ECHI 92236#define SRST_HOST1_ECHI 93237#define SRST_HOST2_ECHI 94238#define SRST_VOP_NOC_A 95239 240#define SRST_HDMI_P 96241#define SRST_VIO_ARBI_H 97242#define SRST_IEP_NOC_A 98243#define SRST_VIO_NOC_H 99244#define SRST_VOP_A 100245#define SRST_VOP_H 101246#define SRST_VOP_D 102247#define SRST_UTMI0 103248#define SRST_UTMI1 104249#define SRST_UTMI2 105250#define SRST_UTMI3 106251#define SRST_RGA 107252#define SRST_RGA_NOC_A 108253#define SRST_RGA_A 109254#define SRST_RGA_H 110255#define SRST_HDCP_A 111256 257#define SRST_VPU_A 112258#define SRST_VPU_H 113259#define SRST_VPU_NOC_A 116260#define SRST_VPU_NOC_H 117261#define SRST_RKVDEC_A 118262#define SRST_RKVDEC_NOC_A 119263#define SRST_RKVDEC_H 120264#define SRST_RKVDEC_NOC_H 121265#define SRST_RKVDEC_CORE 122266#define SRST_RKVDEC_CABAC 123267#define SRST_IEP_A 124268#define SRST_IEP_H 125269#define SRST_GPU_A 126270#define SRST_GPU_NOC_A 127271 272#define SRST_CORE_DBG 128273#define SRST_DBG_P 129274#define SRST_TIMER0 130275#define SRST_TIMER1 131276#define SRST_TIMER2 132277#define SRST_TIMER3 133278#define SRST_TIMER4 134279#define SRST_TIMER5 135280#define SRST_VIO_H2P 136281#define SRST_HDMIPHY 139282#define SRST_VDAC 140283#define SRST_TIMER_6CH_P 141284 285#endif286