379 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2014 MundoReader S.L.4 * Author: Heiko Stuebner <heiko@sntech.de>5 */6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H9 10/* core clocks */11#define PLL_APLL 112#define PLL_DPLL 213#define PLL_CPLL 314#define PLL_GPLL 415#define PLL_NPLL 516#define ARMCLK 617 18/* sclk gates (special clocks) */19#define SCLK_GPU 6420#define SCLK_SPI0 6521#define SCLK_SPI1 6622#define SCLK_SPI2 6723#define SCLK_SDMMC 6824#define SCLK_SDIO0 6925#define SCLK_SDIO1 7026#define SCLK_EMMC 7127#define SCLK_TSADC 7228#define SCLK_SARADC 7329#define SCLK_PS2C 7430#define SCLK_NANDC0 7531#define SCLK_NANDC1 7632#define SCLK_UART0 7733#define SCLK_UART1 7834#define SCLK_UART2 7935#define SCLK_UART3 8036#define SCLK_UART4 8137#define SCLK_I2S0 8238#define SCLK_SPDIF 8339#define SCLK_SPDIF8CH 8440#define SCLK_TIMER0 8541#define SCLK_TIMER1 8642#define SCLK_TIMER2 8743#define SCLK_TIMER3 8844#define SCLK_TIMER4 8945#define SCLK_TIMER5 9046#define SCLK_TIMER6 9147#define SCLK_HSADC 9248#define SCLK_OTGPHY0 9349#define SCLK_OTGPHY1 9450#define SCLK_OTGPHY2 9551#define SCLK_OTG_ADP 9652#define SCLK_HSICPHY480M 9753#define SCLK_HSICPHY12M 9854#define SCLK_MACREF 9955#define SCLK_LCDC_PWM0 10056#define SCLK_LCDC_PWM1 10157#define SCLK_MAC_RX 10258#define SCLK_MAC_TX 10359#define SCLK_EDP_24M 10460#define SCLK_EDP 10561#define SCLK_RGA 10662#define SCLK_ISP 10763#define SCLK_ISP_JPE 10864#define SCLK_HDMI_HDCP 10965#define SCLK_HDMI_CEC 11066#define SCLK_HEVC_CABAC 11167#define SCLK_HEVC_CORE 11268#define SCLK_I2S0_OUT 11369#define SCLK_SDMMC_DRV 11470#define SCLK_SDIO0_DRV 11571#define SCLK_SDIO1_DRV 11672#define SCLK_EMMC_DRV 11773#define SCLK_SDMMC_SAMPLE 11874#define SCLK_SDIO0_SAMPLE 11975#define SCLK_SDIO1_SAMPLE 12076#define SCLK_EMMC_SAMPLE 12177#define SCLK_USBPHY480M_SRC 12278#define SCLK_PVTM_CORE 12379#define SCLK_PVTM_GPU 12480#define SCLK_CRYPTO 12581#define SCLK_MIPIDSI_24M 12682#define SCLK_VIP_OUT 12783 84#define SCLK_MAC 15185#define SCLK_MACREF_OUT 15286 87#define DCLK_VOP0 19088#define DCLK_VOP1 19189 90/* aclk gates */91#define ACLK_GPU 19292#define ACLK_DMAC1 19393#define ACLK_DMAC2 19494#define ACLK_MMU 19595#define ACLK_GMAC 19696#define ACLK_VOP0 19797#define ACLK_VOP1 19898#define ACLK_CRYPTO 19999#define ACLK_RGA 200100#define ACLK_RGA_NIU 201101#define ACLK_IEP 202102#define ACLK_VIO0_NIU 203103#define ACLK_VIP 204104#define ACLK_ISP 205105#define ACLK_VIO1_NIU 206106#define ACLK_HEVC 207107#define ACLK_VCODEC 208108#define ACLK_CPU 209109#define ACLK_PERI 210110 111/* pclk gates */112#define PCLK_GPIO0 320113#define PCLK_GPIO1 321114#define PCLK_GPIO2 322115#define PCLK_GPIO3 323116#define PCLK_GPIO4 324117#define PCLK_GPIO5 325118#define PCLK_GPIO6 326119#define PCLK_GPIO7 327120#define PCLK_GPIO8 328121#define PCLK_GRF 329122#define PCLK_SGRF 330123#define PCLK_PMU 331124#define PCLK_I2C0 332125#define PCLK_I2C1 333126#define PCLK_I2C2 334127#define PCLK_I2C3 335128#define PCLK_I2C4 336129#define PCLK_I2C5 337130#define PCLK_SPI0 338131#define PCLK_SPI1 339132#define PCLK_SPI2 340133#define PCLK_UART0 341134#define PCLK_UART1 342135#define PCLK_UART2 343136#define PCLK_UART3 344137#define PCLK_UART4 345138#define PCLK_TSADC 346139#define PCLK_SARADC 347140#define PCLK_SIM 348141#define PCLK_GMAC 349142#define PCLK_PWM 350143#define PCLK_RKPWM 351144#define PCLK_PS2C 352145#define PCLK_TIMER 353146#define PCLK_TZPC 354147#define PCLK_EDP_CTRL 355148#define PCLK_MIPI_DSI0 356149#define PCLK_MIPI_DSI1 357150#define PCLK_MIPI_CSI 358151#define PCLK_LVDS_PHY 359152#define PCLK_HDMI_CTRL 360153#define PCLK_VIO2_H2P 361154#define PCLK_CPU 362155#define PCLK_PERI 363156#define PCLK_DDRUPCTL0 364157#define PCLK_PUBL0 365158#define PCLK_DDRUPCTL1 366159#define PCLK_PUBL1 367160#define PCLK_WDT 368161#define PCLK_EFUSE256 369162#define PCLK_EFUSE1024 370163#define PCLK_ISP_IN 371164 165/* hclk gates */166#define HCLK_GPS 448167#define HCLK_OTG0 449168#define HCLK_USBHOST0 450169#define HCLK_USBHOST1 451170#define HCLK_HSIC 452171#define HCLK_NANDC0 453172#define HCLK_NANDC1 454173#define HCLK_TSP 455174#define HCLK_SDMMC 456175#define HCLK_SDIO0 457176#define HCLK_SDIO1 458177#define HCLK_EMMC 459178#define HCLK_HSADC 460179#define HCLK_CRYPTO 461180#define HCLK_I2S0 462181#define HCLK_SPDIF 463182#define HCLK_SPDIF8CH 464183#define HCLK_VOP0 465184#define HCLK_VOP1 466185#define HCLK_ROM 467186#define HCLK_IEP 468187#define HCLK_ISP 469188#define HCLK_RGA 470189#define HCLK_VIO_AHB_ARBI 471190#define HCLK_VIO_NIU 472191#define HCLK_VIP 473192#define HCLK_VIO2_H2P 474193#define HCLK_HEVC 475194#define HCLK_VCODEC 476195#define HCLK_CPU 477196#define HCLK_PERI 478197 198/* soft-reset indices */199#define SRST_CORE0 0200#define SRST_CORE1 1201#define SRST_CORE2 2202#define SRST_CORE3 3203#define SRST_CORE0_PO 4204#define SRST_CORE1_PO 5205#define SRST_CORE2_PO 6206#define SRST_CORE3_PO 7207#define SRST_PDCORE_STRSYS 8208#define SRST_PDBUS_STRSYS 9209#define SRST_L2C 10210#define SRST_TOPDBG 11211#define SRST_CORE0_DBG 12212#define SRST_CORE1_DBG 13213#define SRST_CORE2_DBG 14214#define SRST_CORE3_DBG 15215 216#define SRST_PDBUG_AHB_ARBITOR 16217#define SRST_EFUSE256 17218#define SRST_DMAC1 18219#define SRST_INTMEM 19220#define SRST_ROM 20221#define SRST_SPDIF8CH 21222#define SRST_TIMER 22223#define SRST_I2S0 23224#define SRST_SPDIF 24225#define SRST_TIMER0 25226#define SRST_TIMER1 26227#define SRST_TIMER2 27228#define SRST_TIMER3 28229#define SRST_TIMER4 29230#define SRST_TIMER5 30231#define SRST_EFUSE 31232 233#define SRST_GPIO0 32234#define SRST_GPIO1 33235#define SRST_GPIO2 34236#define SRST_GPIO3 35237#define SRST_GPIO4 36238#define SRST_GPIO5 37239#define SRST_GPIO6 38240#define SRST_GPIO7 39241#define SRST_GPIO8 40242#define SRST_I2C0 42243#define SRST_I2C1 43244#define SRST_I2C2 44245#define SRST_I2C3 45246#define SRST_I2C4 46247#define SRST_I2C5 47248 249#define SRST_DWPWM 48250#define SRST_MMC_PERI 49251#define SRST_PERIPH_MMU 50252#define SRST_DAP 51253#define SRST_DAP_SYS 52254#define SRST_TPIU 53255#define SRST_PMU_APB 54256#define SRST_GRF 55257#define SRST_PMU 56258#define SRST_PERIPH_AXI 57259#define SRST_PERIPH_AHB 58260#define SRST_PERIPH_APB 59261#define SRST_PERIPH_NIU 60262#define SRST_PDPERI_AHB_ARBI 61263#define SRST_EMEM 62264#define SRST_USB_PERI 63265 266#define SRST_DMAC2 64267#define SRST_MAC 66268#define SRST_GPS 67269#define SRST_RKPWM 69270#define SRST_CCP 71271#define SRST_USBHOST0 72272#define SRST_HSIC 73273#define SRST_HSIC_AUX 74274#define SRST_HSIC_PHY 75275#define SRST_HSADC 76276#define SRST_NANDC0 77277#define SRST_NANDC1 78278 279#define SRST_TZPC 80280#define SRST_SPI0 83281#define SRST_SPI1 84282#define SRST_SPI2 85283#define SRST_SARADC 87284#define SRST_PDALIVE_NIU 88285#define SRST_PDPMU_INTMEM 89286#define SRST_PDPMU_NIU 90287#define SRST_SGRF 91288 289#define SRST_VIO_ARBI 96290#define SRST_RGA_NIU 97291#define SRST_VIO0_NIU_AXI 98292#define SRST_VIO_NIU_AHB 99293#define SRST_LCDC0_AXI 100294#define SRST_LCDC0_AHB 101295#define SRST_LCDC0_DCLK 102296#define SRST_VIO1_NIU_AXI 103297#define SRST_VIP 104298#define SRST_RGA_CORE 105299#define SRST_IEP_AXI 106300#define SRST_IEP_AHB 107301#define SRST_RGA_AXI 108302#define SRST_RGA_AHB 109303#define SRST_ISP 110304#define SRST_EDP 111305 306#define SRST_VCODEC_AXI 112307#define SRST_VCODEC_AHB 113308#define SRST_VIO_H2P 114309#define SRST_MIPIDSI0 115310#define SRST_MIPIDSI1 116311#define SRST_MIPICSI 117312#define SRST_LVDS_PHY 118313#define SRST_LVDS_CON 119314#define SRST_GPU 120315#define SRST_HDMI 121316#define SRST_CORE_PVTM 124317#define SRST_GPU_PVTM 125318 319#define SRST_MMC0 128320#define SRST_SDIO0 129321#define SRST_SDIO1 130322#define SRST_EMMC 131323#define SRST_USBOTG_AHB 132324#define SRST_USBOTG_PHY 133325#define SRST_USBOTG_CON 134326#define SRST_USBHOST0_AHB 135327#define SRST_USBHOST0_PHY 136328#define SRST_USBHOST0_CON 137329#define SRST_USBHOST1_AHB 138330#define SRST_USBHOST1_PHY 139331#define SRST_USBHOST1_CON 140332#define SRST_USB_ADP 141333#define SRST_ACC_EFUSE 142334 335#define SRST_CORESIGHT 144336#define SRST_PD_CORE_AHB_NOC 145337#define SRST_PD_CORE_APB_NOC 146338#define SRST_PD_CORE_MP_AXI 147339#define SRST_GIC 148340#define SRST_LCDC_PWM0 149341#define SRST_LCDC_PWM1 150342#define SRST_VIO0_H2P_BRG 151343#define SRST_VIO1_H2P_BRG 152344#define SRST_RGA_H2P_BRG 153345#define SRST_HEVC 154346#define SRST_TSADC 159347 348#define SRST_DDRPHY0 160349#define SRST_DDRPHY0_APB 161350#define SRST_DDRCTRL0 162351#define SRST_DDRCTRL0_APB 163352#define SRST_DDRPHY0_CTRL 164353#define SRST_DDRPHY1 165354#define SRST_DDRPHY1_APB 166355#define SRST_DDRCTRL1 167356#define SRST_DDRCTRL1_APB 168357#define SRST_DDRPHY1_CTRL 169358#define SRST_DDRMSCH0 170359#define SRST_DDRMSCH1 171360#define SRST_CRYPTO 174361#define SRST_C2C_HOST 175362 363#define SRST_LCDC1_AXI 176364#define SRST_LCDC1_AHB 177365#define SRST_LCDC1_DCLK 178366#define SRST_UART0 179367#define SRST_UART1 180368#define SRST_UART2 181369#define SRST_UART3 182370#define SRST_UART4 183371#define SRST_SIMC 186372#define SRST_PS2C 187373#define SRST_TSP 188374#define SRST_TSP_CLKIN0 189375#define SRST_TSP_CLKIN1 190376#define SRST_TSP_27M 191377 378#endif379