386 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd.4 * Author: Finley Xiao <finley.xiao@rock-chips.com>5 */6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H9 10/* core clocks */11#define PLL_APLL 112#define PLL_DPLL 213#define PLL_VPLL0 314#define PLL_VPLL1 415#define ARMCLK 516 17/* sclk (special clocks) */18#define USB480M 1419#define SCLK_RTC32K 1520#define SCLK_PVTM_CORE 1621#define SCLK_UART0 1722#define SCLK_UART1 1823#define SCLK_UART2 1924#define SCLK_UART3 2025#define SCLK_UART4 2126#define SCLK_I2C0 2227#define SCLK_I2C1 2328#define SCLK_I2C2 2429#define SCLK_I2C3 2530#define SCLK_PWM0 2631#define SCLK_SPI0 2732#define SCLK_SPI1 2833#define SCLK_SPI2 2934#define SCLK_TIMER0 3035#define SCLK_TIMER1 3136#define SCLK_TIMER2 3237#define SCLK_TIMER3 3338#define SCLK_TIMER4 3439#define SCLK_TIMER5 3540#define SCLK_TSADC 3641#define SCLK_SARADC 3742#define SCLK_OTP 3843#define SCLK_OTP_USR 3944#define SCLK_CPU_BOOST 4045#define SCLK_CRYPTO 4146#define SCLK_CRYPTO_APK 4247#define SCLK_NANDC_DIV 4348#define SCLK_NANDC_DIV50 4449#define SCLK_NANDC 4550#define SCLK_SDMMC_DIV 4651#define SCLK_SDMMC_DIV50 4752#define SCLK_SDMMC 4853#define SCLK_SDMMC_DRV 4954#define SCLK_SDMMC_SAMPLE 5055#define SCLK_SDIO_DIV 5156#define SCLK_SDIO_DIV50 5257#define SCLK_SDIO 5358#define SCLK_SDIO_DRV 5459#define SCLK_SDIO_SAMPLE 5560#define SCLK_EMMC_DIV 5661#define SCLK_EMMC_DIV50 5762#define SCLK_EMMC 5863#define SCLK_EMMC_DRV 5964#define SCLK_EMMC_SAMPLE 6065#define SCLK_SFC 6166#define SCLK_OTG_ADP 6267#define SCLK_MAC_SRC 6368#define SCLK_MAC 6469#define SCLK_MAC_REF 6570#define SCLK_MAC_RX_TX 6671#define SCLK_MAC_RMII 6772#define SCLK_DDR_MON_TIMER 6873#define SCLK_DDR_MON 6974#define SCLK_DDRCLK 7075#define SCLK_PMU 7176#define SCLK_USBPHY_REF 7277#define SCLK_WIFI 7378#define SCLK_PVTM_PMU 7479#define SCLK_PDM 7580#define SCLK_I2S0_8CH_TX 7681#define SCLK_I2S0_8CH_TX_OUT 7782#define SCLK_I2S0_8CH_RX 7883#define SCLK_I2S0_8CH_RX_OUT 7984#define SCLK_I2S1_8CH_TX 8085#define SCLK_I2S1_8CH_TX_OUT 8186#define SCLK_I2S1_8CH_RX 8287#define SCLK_I2S1_8CH_RX_OUT 8388#define SCLK_I2S2_8CH_TX 8489#define SCLK_I2S2_8CH_TX_OUT 8590#define SCLK_I2S2_8CH_RX 8691#define SCLK_I2S2_8CH_RX_OUT 8792#define SCLK_I2S3_8CH_TX 8893#define SCLK_I2S3_8CH_TX_OUT 8994#define SCLK_I2S3_8CH_RX 9095#define SCLK_I2S3_8CH_RX_OUT 9196#define SCLK_I2S0_2CH 9297#define SCLK_I2S0_2CH_OUT 9398#define SCLK_I2S1_2CH 9499#define SCLK_I2S1_2CH_OUT 95100#define SCLK_SPDIF_TX_DIV 96101#define SCLK_SPDIF_TX_DIV50 97102#define SCLK_SPDIF_TX 98103#define SCLK_SPDIF_RX_DIV 99104#define SCLK_SPDIF_RX_DIV50 100105#define SCLK_SPDIF_RX 101106#define SCLK_I2S0_8CH_TX_MUX 102107#define SCLK_I2S0_8CH_RX_MUX 103108#define SCLK_I2S1_8CH_TX_MUX 104109#define SCLK_I2S1_8CH_RX_MUX 105110#define SCLK_I2S2_8CH_TX_MUX 106111#define SCLK_I2S2_8CH_RX_MUX 107112#define SCLK_I2S3_8CH_TX_MUX 108113#define SCLK_I2S3_8CH_RX_MUX 109114#define SCLK_I2S0_8CH_TX_SRC 110115#define SCLK_I2S0_8CH_RX_SRC 111116#define SCLK_I2S1_8CH_TX_SRC 112117#define SCLK_I2S1_8CH_RX_SRC 113118#define SCLK_I2S2_8CH_TX_SRC 114119#define SCLK_I2S2_8CH_RX_SRC 115120#define SCLK_I2S3_8CH_TX_SRC 116121#define SCLK_I2S3_8CH_RX_SRC 117122#define SCLK_I2S0_2CH_SRC 118123#define SCLK_I2S1_2CH_SRC 119124#define SCLK_PWM1 120125#define SCLK_PWM2 121126#define SCLK_OWIRE 122127 128/* dclk */129#define DCLK_VOP 125130 131/* aclk */132#define ACLK_BUS_SRC 130133#define ACLK_BUS 131134#define ACLK_PERI_SRC 132135#define ACLK_PERI 133136#define ACLK_MAC 134137#define ACLK_CRYPTO 135138#define ACLK_VOP 136139#define ACLK_GIC 137140#define ACLK_DMAC0 138141#define ACLK_DMAC1 139142 143/* hclk */144#define HCLK_BUS 150145#define HCLK_PERI 151146#define HCLK_AUDIO 152147#define HCLK_NANDC 153148#define HCLK_SDMMC 154149#define HCLK_SDIO 155150#define HCLK_EMMC 156151#define HCLK_SFC 157152#define HCLK_OTG 158153#define HCLK_HOST 159154#define HCLK_HOST_ARB 160155#define HCLK_PDM 161156#define HCLK_SPDIFTX 162157#define HCLK_SPDIFRX 163158#define HCLK_I2S0_8CH 164159#define HCLK_I2S1_8CH 165160#define HCLK_I2S2_8CH 166161#define HCLK_I2S3_8CH 167162#define HCLK_I2S0_2CH 168163#define HCLK_I2S1_2CH 169164#define HCLK_VAD 170165#define HCLK_CRYPTO 171166#define HCLK_VOP 172167 168/* pclk */169#define PCLK_BUS 190170#define PCLK_DDR 191171#define PCLK_PERI 192172#define PCLK_PMU 193173#define PCLK_AUDIO 194174#define PCLK_MAC 195175#define PCLK_ACODEC 196176#define PCLK_UART0 197177#define PCLK_UART1 198178#define PCLK_UART2 199179#define PCLK_UART3 200180#define PCLK_UART4 201181#define PCLK_I2C0 202182#define PCLK_I2C1 203183#define PCLK_I2C2 204184#define PCLK_I2C3 205185#define PCLK_PWM0 206186#define PCLK_SPI0 207187#define PCLK_SPI1 208188#define PCLK_SPI2 209189#define PCLK_SARADC 210190#define PCLK_TSADC 211191#define PCLK_TIMER 212192#define PCLK_OTP_NS 213193#define PCLK_WDT 214194#define PCLK_GPIO0 215195#define PCLK_GPIO1 216196#define PCLK_GPIO2 217197#define PCLK_GPIO3 218198#define PCLK_GPIO4 219199#define PCLK_SGRF 220200#define PCLK_GRF 221201#define PCLK_USBSD_DET 222202#define PCLK_DDR_UPCTL 223203#define PCLK_DDR_MON 224204#define PCLK_DDRPHY 225205#define PCLK_DDR_STDBY 226206#define PCLK_USB_GRF 227207#define PCLK_CRU 228208#define PCLK_OTP_PHY 229209#define PCLK_CPU_BOOST 230210#define PCLK_PWM1 231211#define PCLK_PWM2 232212#define PCLK_CAN 233213#define PCLK_OWIRE 234214 215/* soft-reset indices */216 217/* cru_softrst_con0 */218#define SRST_CORE0_PO 0219#define SRST_CORE1_PO 1220#define SRST_CORE2_PO 2221#define SRST_CORE3_PO 3222#define SRST_CORE0 4223#define SRST_CORE1 5224#define SRST_CORE2 6225#define SRST_CORE3 7226#define SRST_CORE0_DBG 8227#define SRST_CORE1_DBG 9228#define SRST_CORE2_DBG 10229#define SRST_CORE3_DBG 11230#define SRST_TOPDBG 12231#define SRST_CORE_NOC 13232#define SRST_STRC_A 14233#define SRST_L2C 15234 235/* cru_softrst_con1 */236#define SRST_DAP 16237#define SRST_CORE_PVTM 17238#define SRST_CORE_PRF 18239#define SRST_CORE_GRF 19240#define SRST_DDRUPCTL 20241#define SRST_DDRUPCTL_P 22242#define SRST_MSCH 23243#define SRST_DDRMON_P 25244#define SRST_DDRSTDBY_P 26245#define SRST_DDRSTDBY 27246#define SRST_DDRPHY 28247#define SRST_DDRPHY_DIV 29248#define SRST_DDRPHY_P 30249 250/* cru_softrst_con2 */251#define SRST_BUS_NIU_H 32252#define SRST_USB_NIU_P 33253#define SRST_CRYPTO_A 34254#define SRST_CRYPTO_H 35255#define SRST_CRYPTO 36256#define SRST_CRYPTO_APK 37257#define SRST_VOP_A 38258#define SRST_VOP_H 39259#define SRST_VOP_D 40260#define SRST_INTMEM_A 41261#define SRST_ROM_H 42262#define SRST_GIC_A 43263#define SRST_UART0_P 44264#define SRST_UART0 45265#define SRST_UART1_P 46266#define SRST_UART1 47267 268/* cru_softrst_con3 */269#define SRST_UART2_P 48270#define SRST_UART2 49271#define SRST_UART3_P 50272#define SRST_UART3 51273#define SRST_UART4_P 52274#define SRST_UART4 53275#define SRST_I2C0_P 54276#define SRST_I2C0 55277#define SRST_I2C1_P 56278#define SRST_I2C1 57279#define SRST_I2C2_P 58280#define SRST_I2C2 59281#define SRST_I2C3_P 60282#define SRST_I2C3 61283#define SRST_PWM0_P 62284#define SRST_PWM0 63285 286/* cru_softrst_con4 */287#define SRST_SPI0_P 64288#define SRST_SPI0 65289#define SRST_SPI1_P 66290#define SRST_SPI1 67291#define SRST_SPI2_P 68292#define SRST_SPI2 69293#define SRST_SARADC_P 70294#define SRST_TSADC_P 71295#define SRST_TSADC 72296#define SRST_TIMER0_P 73297#define SRST_TIMER0 74298#define SRST_TIMER1 75299#define SRST_TIMER2 76300#define SRST_TIMER3 77301#define SRST_TIMER4 78302#define SRST_TIMER5 79303 304/* cru_softrst_con5 */305#define SRST_OTP_NS_P 80306#define SRST_OTP_NS_SBPI 81307#define SRST_OTP_NS_USR 82308#define SRST_OTP_PHY_P 83309#define SRST_OTP_PHY 84310#define SRST_GPIO0_P 86311#define SRST_GPIO1_P 87312#define SRST_GPIO2_P 88313#define SRST_GPIO3_P 89314#define SRST_GPIO4_P 90315#define SRST_GRF_P 91316#define SRST_USBSD_DET_P 92317#define SRST_PMU 93318#define SRST_PMU_PVTM 94319#define SRST_USB_GRF_P 95320 321/* cru_softrst_con6 */322#define SRST_CPU_BOOST 96323#define SRST_CPU_BOOST_P 97324#define SRST_PWM1_P 98325#define SRST_PWM1 99326#define SRST_PWM2_P 100327#define SRST_PWM2 101328#define SRST_PERI_NIU_A 104329#define SRST_PERI_NIU_H 105330#define SRST_PERI_NIU_p 106331#define SRST_USB2OTG_H 107332#define SRST_USB2OTG 108333#define SRST_USB2OTG_ADP 109334#define SRST_USB2HOST_H 110335#define SRST_USB2HOST_ARB_H 111336 337/* cru_softrst_con7 */338#define SRST_USB2HOST_AUX_H 112339#define SRST_USB2HOST_EHCI 113340#define SRST_USB2HOST 114341#define SRST_USBPHYPOR 115342#define SRST_UTMI0 116343#define SRST_UTMI1 117344#define SRST_SDIO_H 118345#define SRST_EMMC_H 119346#define SRST_SFC_H 120347#define SRST_SFC 121348#define SRST_SD_H 122349#define SRST_NANDC_H 123350#define SRST_NANDC_N 124351#define SRST_MAC_A 125352#define SRST_CAN_P 126353#define SRST_OWIRE_P 127354 355/* cru_softrst_con8 */356#define SRST_AUDIO_NIU_H 128357#define SRST_AUDIO_NIU_P 129358#define SRST_PDM_H 130359#define SRST_PDM_M 131360#define SRST_SPDIFTX_H 132361#define SRST_SPDIFTX_M 133362#define SRST_SPDIFRX_H 134363#define SRST_SPDIFRX_M 135364#define SRST_I2S0_8CH_H 136365#define SRST_I2S0_8CH_TX_M 137366#define SRST_I2S0_8CH_RX_M 138367#define SRST_I2S1_8CH_H 139368#define SRST_I2S1_8CH_TX_M 140369#define SRST_I2S1_8CH_RX_M 141370#define SRST_I2S2_8CH_H 142371#define SRST_I2S2_8CH_TX_M 143372 373/* cru_softrst_con9 */374#define SRST_I2S2_8CH_RX_M 144375#define SRST_I2S3_8CH_H 145376#define SRST_I2S3_8CH_TX_M 146377#define SRST_I2S3_8CH_RX_M 147378#define SRST_I2S0_2CH_H 148379#define SRST_I2S0_2CH_M 149380#define SRST_I2S1_2CH_H 150381#define SRST_I2S1_2CH_M 151382#define SRST_VAD_H 152383#define SRST_ACODEC_P 153384 385#endif386