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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>4 */5 6#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H7#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H8 9/* core clocks */10#define PLL_APLLB 111#define PLL_APLLL 212#define PLL_DPLL 313#define PLL_CPLL 414#define PLL_GPLL 515#define PLL_NPLL 616#define ARMCLKB 717#define ARMCLKL 818 19/* sclk gates (special clocks) */20#define SCLK_GPU_CORE 6421#define SCLK_SPI0 6522#define SCLK_SPI1 6623#define SCLK_SPI2 6724#define SCLK_SDMMC 6825#define SCLK_SDIO0 6926#define SCLK_EMMC 7127#define SCLK_TSADC 7228#define SCLK_SARADC 7329#define SCLK_NANDC0 7530#define SCLK_UART0 7731#define SCLK_UART1 7832#define SCLK_UART2 7933#define SCLK_UART3 8034#define SCLK_UART4 8135#define SCLK_I2S_8CH 8236#define SCLK_SPDIF_8CH 8337#define SCLK_I2S_2CH 8438#define SCLK_TIMER00 8539#define SCLK_TIMER01 8640#define SCLK_TIMER02 8741#define SCLK_TIMER03 8842#define SCLK_TIMER04 8943#define SCLK_TIMER05 9044#define SCLK_OTGPHY0 9345#define SCLK_OTG_ADP 9646#define SCLK_HSICPHY480M 9747#define SCLK_HSICPHY12M 9848#define SCLK_MACREF 9949#define SCLK_VOP0_PWM 10050#define SCLK_MAC_RX 10251#define SCLK_MAC_TX 10352#define SCLK_EDP_24M 10453#define SCLK_EDP 10554#define SCLK_RGA 10655#define SCLK_ISP 10756#define SCLK_HDCP 10857#define SCLK_HDMI_HDCP 10958#define SCLK_HDMI_CEC 11059#define SCLK_HEVC_CABAC 11160#define SCLK_HEVC_CORE 11261#define SCLK_I2S_8CH_OUT 11362#define SCLK_SDMMC_DRV 11463#define SCLK_SDIO0_DRV 11564#define SCLK_EMMC_DRV 11765#define SCLK_SDMMC_SAMPLE 11866#define SCLK_SDIO0_SAMPLE 11967#define SCLK_EMMC_SAMPLE 12168#define SCLK_USBPHY480M 12269#define SCLK_PVTM_CORE 12370#define SCLK_PVTM_GPU 12471#define SCLK_PVTM_PMU 12572#define SCLK_SFC 12673#define SCLK_MAC 12774#define SCLK_MACREF_OUT 12875#define SCLK_TIMER10 13376#define SCLK_TIMER11 13477#define SCLK_TIMER12 13578#define SCLK_TIMER13 13679#define SCLK_TIMER14 13780#define SCLK_TIMER15 13881#define SCLK_VIP_OUT 13982 83#define DCLK_VOP 19084#define MCLK_CRYPTO 19185 86/* aclk gates */87#define ACLK_GPU_MEM 19288#define ACLK_GPU_CFG 19389#define ACLK_DMAC_BUS 19490#define ACLK_DMAC_PERI 19591#define ACLK_PERI_MMU 19692#define ACLK_GMAC 19793#define ACLK_VOP 19894#define ACLK_VOP_IEP 19995#define ACLK_RGA 20096#define ACLK_HDCP 20197#define ACLK_IEP 20298#define ACLK_VIO0_NOC 20399#define ACLK_VIP 204100#define ACLK_ISP 205101#define ACLK_VIO1_NOC 206102#define ACLK_VIDEO 208103#define ACLK_BUS 209104#define ACLK_PERI 210105 106/* pclk gates */107#define PCLK_GPIO0 320108#define PCLK_GPIO1 321109#define PCLK_GPIO2 322110#define PCLK_GPIO3 323111#define PCLK_PMUGRF 324112#define PCLK_MAILBOX 325113#define PCLK_GRF 329114#define PCLK_SGRF 330115#define PCLK_PMU 331116#define PCLK_I2C0 332117#define PCLK_I2C1 333118#define PCLK_I2C2 334119#define PCLK_I2C3 335120#define PCLK_I2C4 336121#define PCLK_I2C5 337122#define PCLK_SPI0 338123#define PCLK_SPI1 339124#define PCLK_SPI2 340125#define PCLK_UART0 341126#define PCLK_UART1 342127#define PCLK_UART2 343128#define PCLK_UART3 344129#define PCLK_UART4 345130#define PCLK_TSADC 346131#define PCLK_SARADC 347132#define PCLK_SIM 348133#define PCLK_GMAC 349134#define PCLK_PWM0 350135#define PCLK_PWM1 351136#define PCLK_TIMER0 353137#define PCLK_TIMER1 354138#define PCLK_EDP_CTRL 355139#define PCLK_MIPI_DSI0 356140#define PCLK_MIPI_CSI 358141#define PCLK_HDCP 359142#define PCLK_HDMI_CTRL 360143#define PCLK_VIO_H2P 361144#define PCLK_BUS 362145#define PCLK_PERI 363146#define PCLK_DDRUPCTL 364147#define PCLK_DDRPHY 365148#define PCLK_ISP 366149#define PCLK_VIP 367150#define PCLK_WDT 368151#define PCLK_EFUSE256 369152#define PCLK_DPHYRX 370153#define PCLK_DPHYTX0 371154 155/* hclk gates */156#define HCLK_SFC 448157#define HCLK_OTG0 449158#define HCLK_HOST0 450159#define HCLK_HOST1 451160#define HCLK_HSIC 452161#define HCLK_NANDC0 453162#define HCLK_TSP 455163#define HCLK_SDMMC 456164#define HCLK_SDIO0 457165#define HCLK_EMMC 459166#define HCLK_HSADC 460167#define HCLK_CRYPTO 461168#define HCLK_I2S_2CH 462169#define HCLK_I2S_8CH 463170#define HCLK_SPDIF 464171#define HCLK_VOP 465172#define HCLK_ROM 467173#define HCLK_IEP 468174#define HCLK_ISP 469175#define HCLK_RGA 470176#define HCLK_VIO_AHB_ARBI 471177#define HCLK_VIO_NOC 472178#define HCLK_VIP 473179#define HCLK_VIO_H2P 474180#define HCLK_VIO_HDCPMMU 475181#define HCLK_VIDEO 476182#define HCLK_BUS 477183#define HCLK_PERI 478184 185/* soft-reset indices */186#define SRST_CORE_B0 0187#define SRST_CORE_B1 1188#define SRST_CORE_B2 2189#define SRST_CORE_B3 3190#define SRST_CORE_B0_PO 4191#define SRST_CORE_B1_PO 5192#define SRST_CORE_B2_PO 6193#define SRST_CORE_B3_PO 7194#define SRST_L2_B 8195#define SRST_ADB_B 9196#define SRST_PD_CORE_B_NIU 10197#define SRST_PDBUS_STRSYS 11198#define SRST_SOCDBG_B 14199#define SRST_CORE_B_DBG 15200 201#define SRST_DMAC1 18202#define SRST_INTMEM 19203#define SRST_ROM 20204#define SRST_SPDIF8CH 21205#define SRST_I2S8CH 23206#define SRST_MAILBOX 24207#define SRST_I2S2CH 25208#define SRST_EFUSE_256 26209#define SRST_MCU_SYS 28210#define SRST_MCU_PO 29211#define SRST_MCU_NOC 30212#define SRST_EFUSE 31213 214#define SRST_GPIO0 32215#define SRST_GPIO1 33216#define SRST_GPIO2 34217#define SRST_GPIO3 35218#define SRST_GPIO4 36219#define SRST_PMUGRF 41220#define SRST_I2C0 42221#define SRST_I2C1 43222#define SRST_I2C2 44223#define SRST_I2C3 45224#define SRST_I2C4 46225#define SRST_I2C5 47226 227#define SRST_DWPWM 48228#define SRST_MMC_PERI 49229#define SRST_PERIPH_MMU 50230#define SRST_GRF 55231#define SRST_PMU 56232#define SRST_PERIPH_AXI 57233#define SRST_PERIPH_AHB 58234#define SRST_PERIPH_APB 59235#define SRST_PERIPH_NIU 60236#define SRST_PDPERI_AHB_ARBI 61237#define SRST_EMEM 62238#define SRST_USB_PERI 63239 240#define SRST_DMAC2 64241#define SRST_MAC 66242#define SRST_GPS 67243#define SRST_RKPWM 69244#define SRST_USBHOST0 72245#define SRST_HSIC 73246#define SRST_HSIC_AUX 74247#define SRST_HSIC_PHY 75248#define SRST_HSADC 76249#define SRST_NANDC0 77250#define SRST_SFC 79251 252#define SRST_SPI0 83253#define SRST_SPI1 84254#define SRST_SPI2 85255#define SRST_SARADC 87256#define SRST_PDALIVE_NIU 88257#define SRST_PDPMU_INTMEM 89258#define SRST_PDPMU_NIU 90259#define SRST_SGRF 91260 261#define SRST_VIO_ARBI 96262#define SRST_RGA_NIU 97263#define SRST_VIO0_NIU_AXI 98264#define SRST_VIO_NIU_AHB 99265#define SRST_LCDC0_AXI 100266#define SRST_LCDC0_AHB 101267#define SRST_LCDC0_DCLK 102268#define SRST_VIP 104269#define SRST_RGA_CORE 105270#define SRST_IEP_AXI 106271#define SRST_IEP_AHB 107272#define SRST_RGA_AXI 108273#define SRST_RGA_AHB 109274#define SRST_ISP 110275#define SRST_EDP_24M 111276 277#define SRST_VIDEO_AXI 112278#define SRST_VIDEO_AHB 113279#define SRST_MIPIDPHYTX 114280#define SRST_MIPIDSI0 115281#define SRST_MIPIDPHYRX 116282#define SRST_MIPICSI 117283#define SRST_GPU 120284#define SRST_HDMI 121285#define SRST_EDP 122286#define SRST_PMU_PVTM 123287#define SRST_CORE_PVTM 124288#define SRST_GPU_PVTM 125289#define SRST_GPU_SYS 126290#define SRST_GPU_MEM_NIU 127291 292#define SRST_MMC0 128293#define SRST_SDIO0 129294#define SRST_EMMC 131295#define SRST_USBOTG_AHB 132296#define SRST_USBOTG_PHY 133297#define SRST_USBOTG_CON 134298#define SRST_USBHOST0_AHB 135299#define SRST_USBHOST0_PHY 136300#define SRST_USBHOST0_CON 137301#define SRST_USBOTG_UTMI 138302#define SRST_USBHOST1_UTMI 139303#define SRST_USB_ADP 141304 305#define SRST_CORESIGHT 144306#define SRST_PD_CORE_AHB_NOC 145307#define SRST_PD_CORE_APB_NOC 146308#define SRST_GIC 148309#define SRST_LCDC_PWM0 149310#define SRST_RGA_H2P_BRG 153311#define SRST_VIDEO 154312#define SRST_GPU_CFG_NIU 157313#define SRST_TSADC 159314 315#define SRST_DDRPHY0 160316#define SRST_DDRPHY0_APB 161317#define SRST_DDRCTRL0 162318#define SRST_DDRCTRL0_APB 163319#define SRST_VIDEO_NIU 165320#define SRST_VIDEO_NIU_AHB 167321#define SRST_DDRMSCH0 170322#define SRST_PDBUS_AHB 173323#define SRST_CRYPTO 174324 325#define SRST_UART0 179326#define SRST_UART1 180327#define SRST_UART2 181328#define SRST_UART3 182329#define SRST_UART4 183330#define SRST_SIMC 186331#define SRST_TSP 188332#define SRST_TSP_CLKIN0 189333 334#define SRST_CORE_L0 192335#define SRST_CORE_L1 193336#define SRST_CORE_L2 194337#define SRST_CORE_L3 195338#define SRST_CORE_L0_PO 195339#define SRST_CORE_L1_PO 197340#define SRST_CORE_L2_PO 198341#define SRST_CORE_L3_PO 199342#define SRST_L2_L 200343#define SRST_ADB_L 201344#define SRST_PD_CORE_L_NIU 202345#define SRST_CCI_SYS 203346#define SRST_CCI_DDR 204347#define SRST_CCI 205348#define SRST_SOCDBG_L 206349#define SRST_CORE_L_DBG 207350 351#define SRST_CORE_B0_NC 208352#define SRST_CORE_B0_PO_NC 209353#define SRST_L2_B_NC 210354#define SRST_ADB_B_NC 211355#define SRST_PD_CORE_B_NIU_NC 212356#define SRST_PDBUS_STRSYS_NC 213357#define SRST_CORE_L0_NC 214358#define SRST_CORE_L0_PO_NC 215359#define SRST_L2_L_NC 216360#define SRST_ADB_L_NC 217361#define SRST_PD_CORE_L_NIU_NC 218362#define SRST_CCI_SYS_NC 219363#define SRST_CCI_DDR_NC 220364#define SRST_CCI_NC 221365#define SRST_TRACE_NC 222366 367#define SRST_TIMER00 224368#define SRST_TIMER01 225369#define SRST_TIMER02 226370#define SRST_TIMER03 227371#define SRST_TIMER04 228372#define SRST_TIMER05 229373#define SRST_TIMER10 230374#define SRST_TIMER11 231375#define SRST_TIMER12 232376#define SRST_TIMER13 233377#define SRST_TIMER14 234378#define SRST_TIMER15 235379#define SRST_TIMER0_APB 236380#define SRST_TIMER1_APB 237381 382#endif383