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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.4 * Author: Xing Zheng <zhengxing@rock-chips.com>5 */6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H9 10/* core clocks */11#define PLL_APLLL 112#define PLL_APLLB 213#define PLL_DPLL 314#define PLL_CPLL 415#define PLL_GPLL 516#define PLL_NPLL 617#define PLL_VPLL 718#define ARMCLKL 819#define ARMCLKB 920 21/* sclk gates (special clocks) */22#define SCLK_I2C1 6523#define SCLK_I2C2 6624#define SCLK_I2C3 6725#define SCLK_I2C5 6826#define SCLK_I2C6 6927#define SCLK_I2C7 7028#define SCLK_SPI0 7129#define SCLK_SPI1 7230#define SCLK_SPI2 7331#define SCLK_SPI4 7432#define SCLK_SPI5 7533#define SCLK_SDMMC 7634#define SCLK_SDIO 7735#define SCLK_EMMC 7836#define SCLK_TSADC 7937#define SCLK_SARADC 8038#define SCLK_UART0 8139#define SCLK_UART1 8240#define SCLK_UART2 8341#define SCLK_UART3 8442#define SCLK_SPDIF_8CH 8543#define SCLK_I2S0_8CH 8644#define SCLK_I2S1_8CH 8745#define SCLK_I2S2_8CH 8846#define SCLK_I2S_8CH_OUT 8947#define SCLK_TIMER00 9048#define SCLK_TIMER01 9149#define SCLK_TIMER02 9250#define SCLK_TIMER03 9351#define SCLK_TIMER04 9452#define SCLK_TIMER05 9553#define SCLK_TIMER06 9654#define SCLK_TIMER07 9755#define SCLK_TIMER08 9856#define SCLK_TIMER09 9957#define SCLK_TIMER10 10058#define SCLK_TIMER11 10159#define SCLK_MACREF 10260#define SCLK_MAC_RX 10361#define SCLK_MAC_TX 10462#define SCLK_MAC 10563#define SCLK_MACREF_OUT 10664#define SCLK_VOP0_PWM 10765#define SCLK_VOP1_PWM 10866#define SCLK_RGA_CORE 10967#define SCLK_ISP0 11068#define SCLK_ISP1 11169#define SCLK_HDMI_CEC 11270#define SCLK_HDMI_SFR 11371#define SCLK_DP_CORE 11472#define SCLK_PVTM_CORE_L 11573#define SCLK_PVTM_CORE_B 11674#define SCLK_PVTM_GPU 11775#define SCLK_PVTM_DDR 11876#define SCLK_MIPIDPHY_REF 11977#define SCLK_MIPIDPHY_CFG 12078#define SCLK_HSICPHY 12179#define SCLK_USBPHY480M 12280#define SCLK_USB2PHY0_REF 12381#define SCLK_USB2PHY1_REF 12482#define SCLK_UPHY0_TCPDPHY_REF 12583#define SCLK_UPHY0_TCPDCORE 12684#define SCLK_UPHY1_TCPDPHY_REF 12785#define SCLK_UPHY1_TCPDCORE 12886#define SCLK_USB3OTG0_REF 12987#define SCLK_USB3OTG1_REF 13088#define SCLK_USB3OTG0_SUSPEND 13189#define SCLK_USB3OTG1_SUSPEND 13290#define SCLK_CRYPTO0 13391#define SCLK_CRYPTO1 13492#define SCLK_CCI_TRACE 13593#define SCLK_CS 13694#define SCLK_CIF_OUT 13795#define SCLK_PCIEPHY_REF 13896#define SCLK_PCIE_CORE 13997#define SCLK_M0_PERILP 14098#define SCLK_M0_PERILP_DEC 14199#define SCLK_CM0S 142100#define SCLK_DBG_NOC 143101#define SCLK_DBG_PD_CORE_B 144102#define SCLK_DBG_PD_CORE_L 145103#define SCLK_DFIMON0_TIMER 146104#define SCLK_DFIMON1_TIMER 147105#define SCLK_INTMEM0 148106#define SCLK_INTMEM1 149107#define SCLK_INTMEM2 150108#define SCLK_INTMEM3 151109#define SCLK_INTMEM4 152110#define SCLK_INTMEM5 153111#define SCLK_SDMMC_DRV 154112#define SCLK_SDMMC_SAMPLE 155113#define SCLK_SDIO_DRV 156114#define SCLK_SDIO_SAMPLE 157115#define SCLK_VDU_CORE 158116#define SCLK_VDU_CA 159117#define SCLK_PCIE_PM 160118#define SCLK_SPDIF_REC_DPTX 161119#define SCLK_DPHY_PLL 162120#define SCLK_DPHY_TX0_CFG 163121#define SCLK_DPHY_TX1RX1_CFG 164122#define SCLK_DPHY_RX0_CFG 165123#define SCLK_RMII_SRC 166124#define SCLK_PCIEPHY_REF100M 167125#define SCLK_DDRC 168126#define SCLK_TESTCLKOUT1 169127#define SCLK_TESTCLKOUT2 170128 129#define DCLK_VOP0 180130#define DCLK_VOP1 181131#define DCLK_VOP0_DIV 182132#define DCLK_VOP1_DIV 183133#define DCLK_M0_PERILP 184134#define DCLK_VOP0_FRAC 185135#define DCLK_VOP1_FRAC 186136 137#define FCLK_CM0S 190138 139/* aclk gates */140#define ACLK_PERIHP 192141#define ACLK_PERIHP_NOC 193142#define ACLK_PERILP0 194143#define ACLK_PERILP0_NOC 195144#define ACLK_PERF_PCIE 196145#define ACLK_PCIE 197146#define ACLK_INTMEM 198147#define ACLK_TZMA 199148#define ACLK_DCF 200149#define ACLK_CCI 201150#define ACLK_CCI_NOC0 202151#define ACLK_CCI_NOC1 203152#define ACLK_CCI_GRF 204153#define ACLK_CENTER 205154#define ACLK_CENTER_MAIN_NOC 206155#define ACLK_CENTER_PERI_NOC 207156#define ACLK_GPU 208157#define ACLK_PERF_GPU 209158#define ACLK_GPU_GRF 210159#define ACLK_DMAC0_PERILP 211160#define ACLK_DMAC1_PERILP 212161#define ACLK_GMAC 213162#define ACLK_GMAC_NOC 214163#define ACLK_PERF_GMAC 215164#define ACLK_VOP0_NOC 216165#define ACLK_VOP0 217166#define ACLK_VOP1_NOC 218167#define ACLK_VOP1 219168#define ACLK_RGA 220169#define ACLK_RGA_NOC 221170#define ACLK_HDCP 222171#define ACLK_HDCP_NOC 223172#define ACLK_HDCP22 224173#define ACLK_IEP 225174#define ACLK_IEP_NOC 226175#define ACLK_VIO 227176#define ACLK_VIO_NOC 228177#define ACLK_ISP0 229178#define ACLK_ISP1 230179#define ACLK_ISP0_NOC 231180#define ACLK_ISP1_NOC 232181#define ACLK_ISP0_WRAPPER 233182#define ACLK_ISP1_WRAPPER 234183#define ACLK_VCODEC 235184#define ACLK_VCODEC_NOC 236185#define ACLK_VDU 237186#define ACLK_VDU_NOC 238187#define ACLK_PERI 239188#define ACLK_EMMC 240189#define ACLK_EMMC_CORE 241190#define ACLK_EMMC_NOC 242191#define ACLK_EMMC_GRF 243192#define ACLK_USB3 244193#define ACLK_USB3_NOC 245194#define ACLK_USB3OTG0 246195#define ACLK_USB3OTG1 247196#define ACLK_USB3_RKSOC_AXI_PERF 248197#define ACLK_USB3_GRF 249198#define ACLK_GIC 250199#define ACLK_GIC_NOC 251200#define ACLK_GIC_ADB400_CORE_L_2_GIC 252201#define ACLK_GIC_ADB400_CORE_B_2_GIC 253202#define ACLK_GIC_ADB400_GIC_2_CORE_L 254203#define ACLK_GIC_ADB400_GIC_2_CORE_B 255204#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256205#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257206#define ACLK_ADB400M_PD_CORE_L 258207#define ACLK_ADB400M_PD_CORE_B 259208#define ACLK_PERF_CORE_L 260209#define ACLK_PERF_CORE_B 261210#define ACLK_GIC_PRE 262211#define ACLK_VOP0_PRE 263212#define ACLK_VOP1_PRE 264213 214/* pclk gates */215#define PCLK_PERIHP 320216#define PCLK_PERIHP_NOC 321217#define PCLK_PERILP0 322218#define PCLK_PERILP1 323219#define PCLK_PERILP1_NOC 324220#define PCLK_PERILP_SGRF 325221#define PCLK_PERIHP_GRF 326222#define PCLK_PCIE 327223#define PCLK_SGRF 328224#define PCLK_INTR_ARB 329225#define PCLK_CENTER_MAIN_NOC 330226#define PCLK_CIC 331227#define PCLK_COREDBG_B 332228#define PCLK_COREDBG_L 333229#define PCLK_DBG_CXCS_PD_CORE_B 334230#define PCLK_DCF 335231#define PCLK_GPIO2 336232#define PCLK_GPIO3 337233#define PCLK_GPIO4 338234#define PCLK_GRF 339235#define PCLK_HSICPHY 340236#define PCLK_I2C1 341237#define PCLK_I2C2 342238#define PCLK_I2C3 343239#define PCLK_I2C5 344240#define PCLK_I2C6 345241#define PCLK_I2C7 346242#define PCLK_SPI0 347243#define PCLK_SPI1 348244#define PCLK_SPI2 349245#define PCLK_SPI4 350246#define PCLK_SPI5 351247#define PCLK_UART0 352248#define PCLK_UART1 353249#define PCLK_UART2 354250#define PCLK_UART3 355251#define PCLK_TSADC 356252#define PCLK_SARADC 357253#define PCLK_GMAC 358254#define PCLK_GMAC_NOC 359255#define PCLK_TIMER0 360256#define PCLK_TIMER1 361257#define PCLK_EDP 362258#define PCLK_EDP_NOC 363259#define PCLK_EDP_CTRL 364260#define PCLK_VIO 365261#define PCLK_VIO_NOC 366262#define PCLK_VIO_GRF 367263#define PCLK_MIPI_DSI0 368264#define PCLK_MIPI_DSI1 369265#define PCLK_HDCP 370266#define PCLK_HDCP_NOC 371267#define PCLK_HDMI_CTRL 372268#define PCLK_DP_CTRL 373269#define PCLK_HDCP22 374270#define PCLK_GASKET 375271#define PCLK_DDR 376272#define PCLK_DDR_MON 377273#define PCLK_DDR_SGRF 378274#define PCLK_ISP1_WRAPPER 379275#define PCLK_WDT 380276#define PCLK_EFUSE1024NS 381277#define PCLK_EFUSE1024S 382278#define PCLK_PMU_INTR_ARB 383279#define PCLK_MAILBOX0 384280#define PCLK_USBPHY_MUX_G 385281#define PCLK_UPHY0_TCPHY_G 386282#define PCLK_UPHY0_TCPD_G 387283#define PCLK_UPHY1_TCPHY_G 388284#define PCLK_UPHY1_TCPD_G 389285#define PCLK_ALIVE 390286 287/* hclk gates */288#define HCLK_PERIHP 448289#define HCLK_PERILP0 449290#define HCLK_PERILP1 450291#define HCLK_PERILP0_NOC 451292#define HCLK_PERILP1_NOC 452293#define HCLK_M0_PERILP 453294#define HCLK_M0_PERILP_NOC 454295#define HCLK_AHB1TOM 455296#define HCLK_HOST0 456297#define HCLK_HOST0_ARB 457298#define HCLK_HOST1 458299#define HCLK_HOST1_ARB 459300#define HCLK_HSIC 460301#define HCLK_SD 461302#define HCLK_SDMMC 462303#define HCLK_SDMMC_NOC 463304#define HCLK_M_CRYPTO0 464305#define HCLK_M_CRYPTO1 465306#define HCLK_S_CRYPTO0 466307#define HCLK_S_CRYPTO1 467308#define HCLK_I2S0_8CH 468309#define HCLK_I2S1_8CH 469310#define HCLK_I2S2_8CH 470311#define HCLK_SPDIF 471312#define HCLK_VOP0_NOC 472313#define HCLK_VOP0 473314#define HCLK_VOP1_NOC 474315#define HCLK_VOP1 475316#define HCLK_ROM 476317#define HCLK_IEP 477318#define HCLK_IEP_NOC 478319#define HCLK_ISP0 479320#define HCLK_ISP1 480321#define HCLK_ISP0_NOC 481322#define HCLK_ISP1_NOC 482323#define HCLK_ISP0_WRAPPER 483324#define HCLK_ISP1_WRAPPER 484325#define HCLK_RGA 485326#define HCLK_RGA_NOC 486327#define HCLK_HDCP 487328#define HCLK_HDCP_NOC 488329#define HCLK_HDCP22 489330#define HCLK_VCODEC 490331#define HCLK_VCODEC_NOC 491332#define HCLK_VDU 492333#define HCLK_VDU_NOC 493334#define HCLK_SDIO 494335#define HCLK_SDIO_NOC 495336#define HCLK_SDIOAUDIO_NOC 496337 338/* pmu-clocks indices */339 340#define PLL_PPLL 1341 342#define SCLK_32K_SUSPEND_PMU 2343#define SCLK_SPI3_PMU 3344#define SCLK_TIMER12_PMU 4345#define SCLK_TIMER13_PMU 5346#define SCLK_UART4_PMU 6347#define SCLK_PVTM_PMU 7348#define SCLK_WIFI_PMU 8349#define SCLK_I2C0_PMU 9350#define SCLK_I2C4_PMU 10351#define SCLK_I2C8_PMU 11352 353#define PCLK_SRC_PMU 19354#define PCLK_PMU 20355#define PCLK_PMUGRF_PMU 21356#define PCLK_INTMEM1_PMU 22357#define PCLK_GPIO0_PMU 23358#define PCLK_GPIO1_PMU 24359#define PCLK_SGRF_PMU 25360#define PCLK_NOC_PMU 26361#define PCLK_I2C0_PMU 27362#define PCLK_I2C4_PMU 28363#define PCLK_I2C8_PMU 29364#define PCLK_RKPWM_PMU 30365#define PCLK_SPI3_PMU 31366#define PCLK_TIMER_PMU 32367#define PCLK_MAILBOX_PMU 33368#define PCLK_UART4_PMU 34369#define PCLK_WDT_M0_PMU 35370 371#define FCLK_CM0S_SRC_PMU 44372#define FCLK_CM0S_PMU 45373#define SCLK_CM0S_PMU 46374#define HCLK_CM0S_PMU 47375#define DCLK_CM0S_PMU 48376#define PCLK_INTR_ARB_PMU 49377#define HCLK_NOC_PMU 50378 379/* soft-reset indices */380 381/* cru_softrst_con0 */382#define SRST_CORE_L0 0383#define SRST_CORE_B0 1384#define SRST_CORE_PO_L0 2385#define SRST_CORE_PO_B0 3386#define SRST_L2_L 4387#define SRST_L2_B 5388#define SRST_ADB_L 6389#define SRST_ADB_B 7390#define SRST_A_CCI 8391#define SRST_A_CCIM0_NOC 9392#define SRST_A_CCIM1_NOC 10393#define SRST_DBG_NOC 11394 395/* cru_softrst_con1 */396#define SRST_CORE_L0_T 16397#define SRST_CORE_L1 17398#define SRST_CORE_L2 18399#define SRST_CORE_L3 19400#define SRST_CORE_PO_L0_T 20401#define SRST_CORE_PO_L1 21402#define SRST_CORE_PO_L2 22403#define SRST_CORE_PO_L3 23404#define SRST_A_ADB400_GIC2COREL 24405#define SRST_A_ADB400_COREL2GIC 25406#define SRST_P_DBG_L 26407#define SRST_L2_L_T 28408#define SRST_ADB_L_T 29409#define SRST_A_RKPERF_L 30410#define SRST_PVTM_CORE_L 31411 412/* cru_softrst_con2 */413#define SRST_CORE_B0_T 32414#define SRST_CORE_B1 33415#define SRST_CORE_PO_B0_T 36416#define SRST_CORE_PO_B1 37417#define SRST_A_ADB400_GIC2COREB 40418#define SRST_A_ADB400_COREB2GIC 41419#define SRST_P_DBG_B 42420#define SRST_L2_B_T 43421#define SRST_ADB_B_T 45422#define SRST_A_RKPERF_B 46423#define SRST_PVTM_CORE_B 47424 425/* cru_softrst_con3 */426#define SRST_A_CCI_T 50427#define SRST_A_CCIM0_NOC_T 51428#define SRST_A_CCIM1_NOC_T 52429#define SRST_A_ADB400M_PD_CORE_B_T 53430#define SRST_A_ADB400M_PD_CORE_L_T 54431#define SRST_DBG_NOC_T 55432#define SRST_DBG_CXCS 56433#define SRST_CCI_TRACE 57434#define SRST_P_CCI_GRF 58435 436/* cru_softrst_con4 */437#define SRST_A_CENTER_MAIN_NOC 64438#define SRST_A_CENTER_PERI_NOC 65439#define SRST_P_CENTER_MAIN 66440#define SRST_P_DDRMON 67441#define SRST_P_CIC 68442#define SRST_P_CENTER_SGRF 69443#define SRST_DDR0_MSCH 70444#define SRST_DDRCFG0_MSCH 71445#define SRST_DDR0 72446#define SRST_DDRPHY0 73447#define SRST_DDR1_MSCH 74448#define SRST_DDRCFG1_MSCH 75449#define SRST_DDR1 76450#define SRST_DDRPHY1 77451#define SRST_DDR_CIC 78452#define SRST_PVTM_DDR 79453 454/* cru_softrst_con5 */455#define SRST_A_VCODEC_NOC 80456#define SRST_A_VCODEC 81457#define SRST_H_VCODEC_NOC 82458#define SRST_H_VCODEC 83459#define SRST_A_VDU_NOC 88460#define SRST_A_VDU 89461#define SRST_H_VDU_NOC 90462#define SRST_H_VDU 91463#define SRST_VDU_CORE 92464#define SRST_VDU_CA 93465 466/* cru_softrst_con6 */467#define SRST_A_IEP_NOC 96468#define SRST_A_VOP_IEP 97469#define SRST_A_IEP 98470#define SRST_H_IEP_NOC 99471#define SRST_H_IEP 100472#define SRST_A_RGA_NOC 102473#define SRST_A_RGA 103474#define SRST_H_RGA_NOC 104475#define SRST_H_RGA 105476#define SRST_RGA_CORE 106477#define SRST_EMMC_NOC 108478#define SRST_EMMC 109479#define SRST_EMMC_GRF 110480 481/* cru_softrst_con7 */482#define SRST_A_PERIHP_NOC 112483#define SRST_P_PERIHP_GRF 113484#define SRST_H_PERIHP_NOC 114485#define SRST_USBHOST0 115486#define SRST_HOSTC0_AUX 116487#define SRST_HOST0_ARB 117488#define SRST_USBHOST1 118489#define SRST_HOSTC1_AUX 119490#define SRST_HOST1_ARB 120491#define SRST_SDIO0 121492#define SRST_SDMMC 122493#define SRST_HSIC 123494#define SRST_HSIC_AUX 124495#define SRST_AHB1TOM 125496#define SRST_P_PERIHP_NOC 126497#define SRST_HSICPHY 127498 499/* cru_softrst_con8 */500#define SRST_A_PCIE 128501#define SRST_P_PCIE 129502#define SRST_PCIE_CORE 130503#define SRST_PCIE_MGMT 131504#define SRST_PCIE_MGMT_STICKY 132505#define SRST_PCIE_PIPE 133506#define SRST_PCIE_PM 134507#define SRST_PCIEPHY 135508#define SRST_A_GMAC_NOC 136509#define SRST_A_GMAC 137510#define SRST_P_GMAC_NOC 138511#define SRST_P_GMAC_GRF 140512#define SRST_HSICPHY_POR 142513#define SRST_HSICPHY_UTMI 143514 515/* cru_softrst_con9 */516#define SRST_USB2PHY0_POR 144517#define SRST_USB2PHY0_UTMI_PORT0 145518#define SRST_USB2PHY0_UTMI_PORT1 146519#define SRST_USB2PHY0_EHCIPHY 147520#define SRST_UPHY0_PIPE_L00 148521#define SRST_UPHY0 149522#define SRST_UPHY0_TCPDPWRUP 150523#define SRST_USB2PHY1_POR 152524#define SRST_USB2PHY1_UTMI_PORT0 153525#define SRST_USB2PHY1_UTMI_PORT1 154526#define SRST_USB2PHY1_EHCIPHY 155527#define SRST_UPHY1_PIPE_L00 156528#define SRST_UPHY1 157529#define SRST_UPHY1_TCPDPWRUP 158530 531/* cru_softrst_con10 */532#define SRST_A_PERILP0_NOC 160533#define SRST_A_DCF 161534#define SRST_GIC500 162535#define SRST_DMAC0_PERILP0 163536#define SRST_DMAC1_PERILP0 164537#define SRST_TZMA 165538#define SRST_INTMEM 166539#define SRST_ADB400_MST0 167540#define SRST_ADB400_MST1 168541#define SRST_ADB400_SLV0 169542#define SRST_ADB400_SLV1 170543#define SRST_H_PERILP0 171544#define SRST_H_PERILP0_NOC 172545#define SRST_ROM 173546#define SRST_CRYPTO0_S 174547#define SRST_CRYPTO0_M 175548 549/* cru_softrst_con11 */550#define SRST_P_DCF 176551#define SRST_CM0S_NOC 177552#define SRST_CM0S 178553#define SRST_CM0S_DBG 179554#define SRST_CM0S_PO 180555#define SRST_CRYPTO0 181556#define SRST_P_PERILP1_SGRF 182557#define SRST_P_PERILP1_GRF 183558#define SRST_CRYPTO1_S 184559#define SRST_CRYPTO1_M 185560#define SRST_CRYPTO1 186561#define SRST_GIC_NOC 188562#define SRST_SD_NOC 189563#define SRST_SDIOAUDIO_BRG 190564 565/* cru_softrst_con12 */566#define SRST_H_PERILP1 192567#define SRST_H_PERILP1_NOC 193568#define SRST_H_I2S0_8CH 194569#define SRST_H_I2S1_8CH 195570#define SRST_H_I2S2_8CH 196571#define SRST_H_SPDIF_8CH 197572#define SRST_P_PERILP1_NOC 198573#define SRST_P_EFUSE_1024 199574#define SRST_P_EFUSE_1024S 200575#define SRST_P_I2C0 201576#define SRST_P_I2C1 202577#define SRST_P_I2C2 203578#define SRST_P_I2C3 204579#define SRST_P_I2C4 205580#define SRST_P_I2C5 206581#define SRST_P_MAILBOX0 207582 583/* cru_softrst_con13 */584#define SRST_P_UART0 208585#define SRST_P_UART1 209586#define SRST_P_UART2 210587#define SRST_P_UART3 211588#define SRST_P_SARADC 212589#define SRST_P_TSADC 213590#define SRST_P_SPI0 214591#define SRST_P_SPI1 215592#define SRST_P_SPI2 216593#define SRST_P_SPI3 217594#define SRST_P_SPI4 218595#define SRST_SPI0 219596#define SRST_SPI1 220597#define SRST_SPI2 221598#define SRST_SPI3 222599#define SRST_SPI4 223600 601/* cru_softrst_con14 */602#define SRST_I2S0_8CH 224603#define SRST_I2S1_8CH 225604#define SRST_I2S2_8CH 226605#define SRST_SPDIF_8CH 227606#define SRST_UART0 228607#define SRST_UART1 229608#define SRST_UART2 230609#define SRST_UART3 231610#define SRST_TSADC 232611#define SRST_I2C0 233612#define SRST_I2C1 234613#define SRST_I2C2 235614#define SRST_I2C3 236615#define SRST_I2C4 237616#define SRST_I2C5 238617#define SRST_SDIOAUDIO_NOC 239618 619/* cru_softrst_con15 */620#define SRST_A_VIO_NOC 240621#define SRST_A_HDCP_NOC 241622#define SRST_A_HDCP 242623#define SRST_H_HDCP_NOC 243624#define SRST_H_HDCP 244625#define SRST_P_HDCP_NOC 245626#define SRST_P_HDCP 246627#define SRST_P_HDMI_CTRL 247628#define SRST_P_DP_CTRL 248629#define SRST_S_DP_CTRL 249630#define SRST_C_DP_CTRL 250631#define SRST_P_MIPI_DSI0 251632#define SRST_P_MIPI_DSI1 252633#define SRST_DP_CORE 253634#define SRST_DP_I2S 254635 636/* cru_softrst_con16 */637#define SRST_GASKET 256638#define SRST_VIO_GRF 258639#define SRST_DPTX_SPDIF_REC 259640#define SRST_HDMI_CTRL 260641#define SRST_HDCP_CTRL 261642#define SRST_A_ISP0_NOC 262643#define SRST_A_ISP1_NOC 263644#define SRST_H_ISP0_NOC 266645#define SRST_H_ISP1_NOC 267646#define SRST_H_ISP0 268647#define SRST_H_ISP1 269648#define SRST_ISP0 270649#define SRST_ISP1 271650 651/* cru_softrst_con17 */652#define SRST_A_VOP0_NOC 272653#define SRST_A_VOP1_NOC 273654#define SRST_A_VOP0 274655#define SRST_A_VOP1 275656#define SRST_H_VOP0_NOC 276657#define SRST_H_VOP1_NOC 277658#define SRST_H_VOP0 278659#define SRST_H_VOP1 279660#define SRST_D_VOP0 280661#define SRST_D_VOP1 281662#define SRST_VOP0_PWM 282663#define SRST_VOP1_PWM 283664#define SRST_P_EDP_NOC 284665#define SRST_P_EDP_CTRL 285666 667/* cru_softrst_con18 */668#define SRST_A_GPU 288669#define SRST_A_GPU_NOC 289670#define SRST_A_GPU_GRF 290671#define SRST_PVTM_GPU 291672#define SRST_A_USB3_NOC 292673#define SRST_A_USB3_OTG0 293674#define SRST_A_USB3_OTG1 294675#define SRST_A_USB3_GRF 295676#define SRST_PMU 296677 678/* cru_softrst_con19 */679#define SRST_P_TIMER0_5 304680#define SRST_TIMER0 305681#define SRST_TIMER1 306682#define SRST_TIMER2 307683#define SRST_TIMER3 308684#define SRST_TIMER4 309685#define SRST_TIMER5 310686#define SRST_P_TIMER6_11 311687#define SRST_TIMER6 312688#define SRST_TIMER7 313689#define SRST_TIMER8 314690#define SRST_TIMER9 315691#define SRST_TIMER10 316692#define SRST_TIMER11 317693#define SRST_P_INTR_ARB_PMU 318694#define SRST_P_ALIVE_SGRF 319695 696/* cru_softrst_con20 */697#define SRST_P_GPIO2 320698#define SRST_P_GPIO3 321699#define SRST_P_GPIO4 322700#define SRST_P_GRF 323701#define SRST_P_ALIVE_NOC 324702#define SRST_P_WDT0 325703#define SRST_P_WDT1 326704#define SRST_P_INTR_ARB 327705#define SRST_P_UPHY0_DPTX 328706#define SRST_P_UPHY0_APB 330707#define SRST_P_UPHY0_TCPHY 332708#define SRST_P_UPHY1_TCPHY 333709#define SRST_P_UPHY0_TCPDCTRL 334710#define SRST_P_UPHY1_TCPDCTRL 335711 712/* pmu soft-reset indices */713 714/* pmu_cru_softrst_con0 */715#define SRST_P_NOC 0716#define SRST_P_INTMEM 1717#define SRST_H_CM0S 2718#define SRST_H_CM0S_NOC 3719#define SRST_DBG_CM0S 4720#define SRST_PO_CM0S 5721#define SRST_P_SPI6 6722#define SRST_SPI6 7723#define SRST_P_TIMER_0_1 8724#define SRST_P_TIMER_0 9725#define SRST_P_TIMER_1 10726#define SRST_P_UART4 11727#define SRST_UART4 12728#define SRST_P_WDT 13729 730/* pmu_cru_softrst_con1 */731#define SRST_P_I2C6 16732#define SRST_P_I2C7 17733#define SRST_P_I2C8 18734#define SRST_P_MAILBOX 19735#define SRST_P_RKPWM 20736#define SRST_P_PMUGRF 21737#define SRST_P_SGRF 22738#define SRST_P_GPIO0 23739#define SRST_P_GPIO1 24740#define SRST_P_CRU 25741#define SRST_P_INTR 26742#define SRST_PVTM 27743#define SRST_I2C6 28744#define SRST_I2C7 29745#define SRST_I2C8 30746 747#endif748