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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.4 * Author: Elaine Zhang <zhangqing@rock-chips.com>5 */6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H9 10/* pmucru-clocks indices */11 12/* pmucru plls */13#define PLL_PPLL 114#define PLL_HPLL 215 16/* pmucru clocks */17#define XIN_OSC0_DIV 418#define CLK_RTC_32K 519#define CLK_PMU 620#define CLK_I2C0 721#define CLK_RTC32K_FRAC 822#define CLK_UART0_DIV 923#define CLK_UART0_FRAC 1024#define SCLK_UART0 1125#define DBCLK_GPIO0 1226#define CLK_PWM0 1327#define CLK_CAPTURE_PWM0_NDFT 1428#define CLK_PMUPVTM 1529#define CLK_CORE_PMUPVTM 1630#define CLK_REF24M 1731#define XIN_OSC0_USBPHY0_G 1832#define CLK_USBPHY0_REF 1933#define XIN_OSC0_USBPHY1_G 2034#define CLK_USBPHY1_REF 2135#define XIN_OSC0_MIPIDSIPHY0_G 2236#define CLK_MIPIDSIPHY0_REF 2337#define XIN_OSC0_MIPIDSIPHY1_G 2438#define CLK_MIPIDSIPHY1_REF 2539#define CLK_WIFI_DIV 2640#define CLK_WIFI_OSC0 2741#define CLK_WIFI 2842#define CLK_PCIEPHY0_DIV 2943#define CLK_PCIEPHY0_OSC0 3044#define CLK_PCIEPHY0_REF 3145#define CLK_PCIEPHY1_DIV 3246#define CLK_PCIEPHY1_OSC0 3347#define CLK_PCIEPHY1_REF 3448#define CLK_PCIEPHY2_DIV 3549#define CLK_PCIEPHY2_OSC0 3650#define CLK_PCIEPHY2_REF 3751#define CLK_PCIE30PHY_REF_M 3852#define CLK_PCIE30PHY_REF_N 3953#define CLK_HDMI_REF 4054#define XIN_OSC0_EDPPHY_G 4155#define PCLK_PDPMU 4256#define PCLK_PMU 4357#define PCLK_UART0 4458#define PCLK_I2C0 4559#define PCLK_GPIO0 4660#define PCLK_PMUPVTM 4761#define PCLK_PWM0 4862#define CLK_PDPMU 4963#define SCLK_32K_IOE 5064 65#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1)66 67/* cru-clocks indices */68 69/* cru plls */70#define PLL_APLL 171#define PLL_DPLL 272#define PLL_CPLL 373#define PLL_GPLL 474#define PLL_VPLL 575#define PLL_NPLL 676 77/* cru clocks */78#define CPLL_333M 979#define ARMCLK 1080#define USB480M 1181#define USB480M_PHY 1282#define ACLK_CORE_NIU2BUS 1883#define CLK_CORE_PVTM 1984#define CLK_CORE_PVTM_CORE 2085#define CLK_CORE_PVTPLL 2186#define CLK_GPU_SRC 2287#define CLK_GPU_PRE_NDFT 2388#define CLK_GPU_PRE_MUX 2489#define ACLK_GPU_PRE 2590#define PCLK_GPU_PRE 2691#define CLK_GPU 2792#define CLK_GPU_NP5 2893#define PCLK_GPU_PVTM 2994#define CLK_GPU_PVTM 3095#define CLK_GPU_PVTM_CORE 3196#define CLK_GPU_PVTPLL 3297#define CLK_NPU_SRC 3398#define CLK_NPU_PRE_NDFT 3499#define CLK_NPU 35100#define CLK_NPU_NP5 36101#define HCLK_NPU_PRE 37102#define PCLK_NPU_PRE 38103#define ACLK_NPU_PRE 39104#define ACLK_NPU 40105#define HCLK_NPU 41106#define PCLK_NPU_PVTM 42107#define CLK_NPU_PVTM 43108#define CLK_NPU_PVTM_CORE 44109#define CLK_NPU_PVTPLL 45110#define CLK_DDRPHY1X_SRC 46111#define CLK_DDRPHY1X_HWFFC_SRC 47112#define CLK_DDR1X 48113#define CLK_MSCH 49114#define CLK24_DDRMON 50115#define ACLK_GIC_AUDIO 51116#define HCLK_GIC_AUDIO 52117#define HCLK_SDMMC_BUFFER 53118#define DCLK_SDMMC_BUFFER 54119#define ACLK_GIC600 55120#define ACLK_SPINLOCK 56121#define HCLK_I2S0_8CH 57122#define HCLK_I2S1_8CH 58123#define HCLK_I2S2_2CH 59124#define HCLK_I2S3_2CH 60125#define CLK_I2S0_8CH_TX_SRC 61126#define CLK_I2S0_8CH_TX_FRAC 62127#define MCLK_I2S0_8CH_TX 63128#define I2S0_MCLKOUT_TX 64129#define CLK_I2S0_8CH_RX_SRC 65130#define CLK_I2S0_8CH_RX_FRAC 66131#define MCLK_I2S0_8CH_RX 67132#define I2S0_MCLKOUT_RX 68133#define CLK_I2S1_8CH_TX_SRC 69134#define CLK_I2S1_8CH_TX_FRAC 70135#define MCLK_I2S1_8CH_TX 71136#define I2S1_MCLKOUT_TX 72137#define CLK_I2S1_8CH_RX_SRC 73138#define CLK_I2S1_8CH_RX_FRAC 74139#define MCLK_I2S1_8CH_RX 75140#define I2S1_MCLKOUT_RX 76141#define CLK_I2S2_2CH_SRC 77142#define CLK_I2S2_2CH_FRAC 78143#define MCLK_I2S2_2CH 79144#define I2S2_MCLKOUT 80145#define CLK_I2S3_2CH_TX_SRC 81146#define CLK_I2S3_2CH_TX_FRAC 82147#define MCLK_I2S3_2CH_TX 83148#define I2S3_MCLKOUT_TX 84149#define CLK_I2S3_2CH_RX_SRC 85150#define CLK_I2S3_2CH_RX_FRAC 86151#define MCLK_I2S3_2CH_RX 87152#define I2S3_MCLKOUT_RX 88153#define HCLK_PDM 89154#define MCLK_PDM 90155#define HCLK_VAD 91156#define HCLK_SPDIF_8CH 92157#define MCLK_SPDIF_8CH_SRC 93158#define MCLK_SPDIF_8CH_FRAC 94159#define MCLK_SPDIF_8CH 95160#define HCLK_AUDPWM 96161#define SCLK_AUDPWM_SRC 97162#define SCLK_AUDPWM_FRAC 98163#define SCLK_AUDPWM 99164#define HCLK_ACDCDIG 100165#define CLK_ACDCDIG_I2C 101166#define CLK_ACDCDIG_DAC 102167#define CLK_ACDCDIG_ADC 103168#define ACLK_SECURE_FLASH 104169#define HCLK_SECURE_FLASH 105170#define ACLK_CRYPTO_NS 106171#define HCLK_CRYPTO_NS 107172#define CLK_CRYPTO_NS_CORE 108173#define CLK_CRYPTO_NS_PKA 109174#define CLK_CRYPTO_NS_RNG 110175#define HCLK_TRNG_NS 111176#define CLK_TRNG_NS 112177#define PCLK_OTPC_NS 113178#define CLK_OTPC_NS_SBPI 114179#define CLK_OTPC_NS_USR 115180#define HCLK_NANDC 116181#define NCLK_NANDC 117182#define HCLK_SFC 118183#define HCLK_SFC_XIP 119184#define SCLK_SFC 120185#define ACLK_EMMC 121186#define HCLK_EMMC 122187#define BCLK_EMMC 123188#define CCLK_EMMC 124189#define TCLK_EMMC 125190#define ACLK_PIPE 126191#define PCLK_PIPE 127192#define PCLK_PIPE_GRF 128193#define ACLK_PCIE20_MST 129194#define ACLK_PCIE20_SLV 130195#define ACLK_PCIE20_DBI 131196#define PCLK_PCIE20 132197#define CLK_PCIE20_AUX_NDFT 133198#define CLK_PCIE20_AUX_DFT 134199#define CLK_PCIE20_PIPE_DFT 135200#define ACLK_PCIE30X1_MST 136201#define ACLK_PCIE30X1_SLV 137202#define ACLK_PCIE30X1_DBI 138203#define PCLK_PCIE30X1 139204#define CLK_PCIE30X1_AUX_NDFT 140205#define CLK_PCIE30X1_AUX_DFT 141206#define CLK_PCIE30X1_PIPE_DFT 142207#define ACLK_PCIE30X2_MST 143208#define ACLK_PCIE30X2_SLV 144209#define ACLK_PCIE30X2_DBI 145210#define PCLK_PCIE30X2 146211#define CLK_PCIE30X2_AUX_NDFT 147212#define CLK_PCIE30X2_AUX_DFT 148213#define CLK_PCIE30X2_PIPE_DFT 149214#define ACLK_SATA0 150215#define CLK_SATA0_PMALIVE 151216#define CLK_SATA0_RXOOB 152217#define CLK_SATA0_PIPE_NDFT 153218#define CLK_SATA0_PIPE_DFT 154219#define ACLK_SATA1 155220#define CLK_SATA1_PMALIVE 156221#define CLK_SATA1_RXOOB 157222#define CLK_SATA1_PIPE_NDFT 158223#define CLK_SATA1_PIPE_DFT 159224#define ACLK_SATA2 160225#define CLK_SATA2_PMALIVE 161226#define CLK_SATA2_RXOOB 162227#define CLK_SATA2_PIPE_NDFT 163228#define CLK_SATA2_PIPE_DFT 164229#define ACLK_USB3OTG0 165230#define CLK_USB3OTG0_REF 166231#define CLK_USB3OTG0_SUSPEND 167232#define ACLK_USB3OTG1 168233#define CLK_USB3OTG1_REF 169234#define CLK_USB3OTG1_SUSPEND 170235#define CLK_XPCS_EEE 171236#define PCLK_XPCS 172237#define ACLK_PHP 173238#define HCLK_PHP 174239#define PCLK_PHP 175240#define HCLK_SDMMC0 176241#define CLK_SDMMC0 177242#define HCLK_SDMMC1 178243#define CLK_SDMMC1 179244#define ACLK_GMAC0 180245#define PCLK_GMAC0 181246#define CLK_MAC0_2TOP 182247#define CLK_MAC0_OUT 183248#define CLK_MAC0_REFOUT 184249#define CLK_GMAC0_PTP_REF 185250#define ACLK_USB 186251#define HCLK_USB 187252#define PCLK_USB 188253#define HCLK_USB2HOST0 189254#define HCLK_USB2HOST0_ARB 190255#define HCLK_USB2HOST1 191256#define HCLK_USB2HOST1_ARB 192257#define HCLK_SDMMC2 193258#define CLK_SDMMC2 194259#define ACLK_GMAC1 195260#define PCLK_GMAC1 196261#define CLK_MAC1_2TOP 197262#define CLK_MAC1_OUT 198263#define CLK_MAC1_REFOUT 199264#define CLK_GMAC1_PTP_REF 200265#define ACLK_PERIMID 201266#define HCLK_PERIMID 202267#define ACLK_VI 203268#define HCLK_VI 204269#define PCLK_VI 205270#define ACLK_VICAP 206271#define HCLK_VICAP 207272#define DCLK_VICAP 208273#define ICLK_VICAP_G 209274#define ACLK_ISP 210275#define HCLK_ISP 211276#define CLK_ISP 212277#define PCLK_CSI2HOST1 213278#define CLK_CIF_OUT 214279#define CLK_CAM0_OUT 215280#define CLK_CAM1_OUT 216281#define ACLK_VO 217282#define HCLK_VO 218283#define PCLK_VO 219284#define ACLK_VOP_PRE 220285#define ACLK_VOP 221286#define HCLK_VOP 222287#define DCLK_VOP0 223288#define DCLK_VOP1 224289#define DCLK_VOP2 225290#define CLK_VOP_PWM 226291#define ACLK_HDCP 227292#define HCLK_HDCP 228293#define PCLK_HDCP 229294#define PCLK_HDMI_HOST 230295#define CLK_HDMI_SFR 231296#define PCLK_DSITX_0 232297#define PCLK_DSITX_1 233298#define PCLK_EDP_CTRL 234299#define CLK_EDP_200M 235300#define ACLK_VPU_PRE 236301#define HCLK_VPU_PRE 237302#define ACLK_VPU 238303#define HCLK_VPU 239304#define ACLK_RGA_PRE 240305#define HCLK_RGA_PRE 241306#define PCLK_RGA_PRE 242307#define ACLK_RGA 243308#define HCLK_RGA 244309#define CLK_RGA_CORE 245310#define ACLK_IEP 246311#define HCLK_IEP 247312#define CLK_IEP_CORE 248313#define HCLK_EBC 249314#define DCLK_EBC 250315#define ACLK_JDEC 251316#define HCLK_JDEC 252317#define ACLK_JENC 253318#define HCLK_JENC 254319#define PCLK_EINK 255320#define HCLK_EINK 256321#define ACLK_RKVENC_PRE 257322#define HCLK_RKVENC_PRE 258323#define ACLK_RKVENC 259324#define HCLK_RKVENC 260325#define CLK_RKVENC_CORE 261326#define ACLK_RKVDEC_PRE 262327#define HCLK_RKVDEC_PRE 263328#define ACLK_RKVDEC 264329#define HCLK_RKVDEC 265330#define CLK_RKVDEC_CA 266331#define CLK_RKVDEC_CORE 267332#define CLK_RKVDEC_HEVC_CA 268333#define ACLK_BUS 269334#define PCLK_BUS 270335#define PCLK_TSADC 271336#define CLK_TSADC_TSEN 272337#define CLK_TSADC 273338#define PCLK_SARADC 274339#define CLK_SARADC 275340#define PCLK_SCR 276341#define PCLK_WDT_NS 277342#define TCLK_WDT_NS 278343#define ACLK_DMAC0 279344#define ACLK_DMAC1 280345#define ACLK_MCU 281346#define PCLK_INTMUX 282347#define PCLK_MAILBOX 283348#define PCLK_UART1 284349#define CLK_UART1_SRC 285350#define CLK_UART1_FRAC 286351#define SCLK_UART1 287352#define PCLK_UART2 288353#define CLK_UART2_SRC 289354#define CLK_UART2_FRAC 290355#define SCLK_UART2 291356#define PCLK_UART3 292357#define CLK_UART3_SRC 293358#define CLK_UART3_FRAC 294359#define SCLK_UART3 295360#define PCLK_UART4 296361#define CLK_UART4_SRC 297362#define CLK_UART4_FRAC 298363#define SCLK_UART4 299364#define PCLK_UART5 300365#define CLK_UART5_SRC 301366#define CLK_UART5_FRAC 302367#define SCLK_UART5 303368#define PCLK_UART6 304369#define CLK_UART6_SRC 305370#define CLK_UART6_FRAC 306371#define SCLK_UART6 307372#define PCLK_UART7 308373#define CLK_UART7_SRC 309374#define CLK_UART7_FRAC 310375#define SCLK_UART7 311376#define PCLK_UART8 312377#define CLK_UART8_SRC 313378#define CLK_UART8_FRAC 314379#define SCLK_UART8 315380#define PCLK_UART9 316381#define CLK_UART9_SRC 317382#define CLK_UART9_FRAC 318383#define SCLK_UART9 319384#define PCLK_CAN0 320385#define CLK_CAN0 321386#define PCLK_CAN1 322387#define CLK_CAN1 323388#define PCLK_CAN2 324389#define CLK_CAN2 325390#define CLK_I2C 326391#define PCLK_I2C1 327392#define CLK_I2C1 328393#define PCLK_I2C2 329394#define CLK_I2C2 330395#define PCLK_I2C3 331396#define CLK_I2C3 332397#define PCLK_I2C4 333398#define CLK_I2C4 334399#define PCLK_I2C5 335400#define CLK_I2C5 336401#define PCLK_SPI0 337402#define CLK_SPI0 338403#define PCLK_SPI1 339404#define CLK_SPI1 340405#define PCLK_SPI2 341406#define CLK_SPI2 342407#define PCLK_SPI3 343408#define CLK_SPI3 344409#define PCLK_PWM1 345410#define CLK_PWM1 346411#define CLK_PWM1_CAPTURE 347412#define PCLK_PWM2 348413#define CLK_PWM2 349414#define CLK_PWM2_CAPTURE 350415#define PCLK_PWM3 351416#define CLK_PWM3 352417#define CLK_PWM3_CAPTURE 353418#define DBCLK_GPIO 354419#define PCLK_GPIO1 355420#define DBCLK_GPIO1 356421#define PCLK_GPIO2 357422#define DBCLK_GPIO2 358423#define PCLK_GPIO3 359424#define DBCLK_GPIO3 360425#define PCLK_GPIO4 361426#define DBCLK_GPIO4 362427#define OCC_SCAN_CLK_GPIO 363428#define PCLK_TIMER 364429#define CLK_TIMER0 365430#define CLK_TIMER1 366431#define CLK_TIMER2 367432#define CLK_TIMER3 368433#define CLK_TIMER4 369434#define CLK_TIMER5 370435#define ACLK_TOP_HIGH 371436#define ACLK_TOP_LOW 372437#define HCLK_TOP 373438#define PCLK_TOP 374439#define PCLK_PCIE30PHY 375440#define CLK_OPTC_ARB 376441#define PCLK_MIPICSIPHY 377442#define PCLK_MIPIDSIPHY0 378443#define PCLK_MIPIDSIPHY1 379444#define PCLK_PIPEPHY0 380445#define PCLK_PIPEPHY1 381446#define PCLK_PIPEPHY2 382447#define PCLK_CPU_BOOST 383448#define CLK_CPU_BOOST 384449#define PCLK_OTPPHY 385450#define SCLK_GMAC0 386451#define SCLK_GMAC0_RGMII_SPEED 387452#define SCLK_GMAC0_RMII_SPEED 388453#define SCLK_GMAC0_RX_TX 389454#define SCLK_GMAC1 390455#define SCLK_GMAC1_RGMII_SPEED 391456#define SCLK_GMAC1_RMII_SPEED 392457#define SCLK_GMAC1_RX_TX 393458#define SCLK_SDMMC0_DRV 394459#define SCLK_SDMMC0_SAMPLE 395460#define SCLK_SDMMC1_DRV 396461#define SCLK_SDMMC1_SAMPLE 397462#define SCLK_SDMMC2_DRV 398463#define SCLK_SDMMC2_SAMPLE 399464#define SCLK_EMMC_DRV 400465#define SCLK_EMMC_SAMPLE 401466#define PCLK_EDPPHY_GRF 402467#define CLK_HDMI_CEC 403468#define CLK_I2S0_8CH_TX 404469#define CLK_I2S0_8CH_RX 405470#define CLK_I2S1_8CH_TX 406471#define CLK_I2S1_8CH_RX 407472#define CLK_I2S2_2CH 408473#define CLK_I2S3_2CH_TX 409474#define CLK_I2S3_2CH_RX 410475#define CPLL_500M 411476#define CPLL_250M 412477#define CPLL_125M 413478#define CPLL_62P5M 414479#define CPLL_50M 415480#define CPLL_25M 416481#define CPLL_100M 417482#define SCLK_DDRCLK 418483 484#define PCLK_CORE_PVTM 450485 486#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)487 488/* pmu soft-reset indices */489/* pmucru_softrst_con0 */490#define SRST_P_PDPMU_NIU 0491#define SRST_P_PMUCRU 1492#define SRST_P_PMUGRF 2493#define SRST_P_I2C0 3494#define SRST_I2C0 4495#define SRST_P_UART0 5496#define SRST_S_UART0 6497#define SRST_P_PWM0 7498#define SRST_PWM0 8499#define SRST_P_GPIO0 9500#define SRST_GPIO0 10501#define SRST_P_PMUPVTM 11502#define SRST_PMUPVTM 12503 504/* soft-reset indices */505 506/* cru_softrst_con0 */507#define SRST_NCORERESET0 0508#define SRST_NCORERESET1 1509#define SRST_NCORERESET2 2510#define SRST_NCORERESET3 3511#define SRST_NCPUPORESET0 4512#define SRST_NCPUPORESET1 5513#define SRST_NCPUPORESET2 6514#define SRST_NCPUPORESET3 7515#define SRST_NSRESET 8516#define SRST_NSPORESET 9517#define SRST_NATRESET 10518#define SRST_NGICRESET 11519#define SRST_NPRESET 12520#define SRST_NPERIPHRESET 13521 522/* cru_softrst_con1 */523#define SRST_A_CORE_NIU2DDR 16524#define SRST_A_CORE_NIU2BUS 17525#define SRST_P_DBG_NIU 18526#define SRST_P_DBG 19527#define SRST_P_DBG_DAPLITE 20528#define SRST_DAP 21529#define SRST_A_ADB400_CORE2GIC 22530#define SRST_A_ADB400_GIC2CORE 23531#define SRST_P_CORE_GRF 24532#define SRST_P_CORE_PVTM 25533#define SRST_CORE_PVTM 26534#define SRST_CORE_PVTPLL 27535 536/* cru_softrst_con2 */537#define SRST_GPU 32538#define SRST_A_GPU_NIU 33539#define SRST_P_GPU_NIU 34540#define SRST_P_GPU_PVTM 35541#define SRST_GPU_PVTM 36542#define SRST_GPU_PVTPLL 37543#define SRST_A_NPU_NIU 40544#define SRST_H_NPU_NIU 41545#define SRST_P_NPU_NIU 42546#define SRST_A_NPU 43547#define SRST_H_NPU 44548#define SRST_P_NPU_PVTM 45549#define SRST_NPU_PVTM 46550#define SRST_NPU_PVTPLL 47551 552/* cru_softrst_con3 */553#define SRST_A_MSCH 51554#define SRST_HWFFC_CTRL 52555#define SRST_DDR_ALWAYSON 53556#define SRST_A_DDRSPLIT 54557#define SRST_DDRDFI_CTL 55558#define SRST_A_DMA2DDR 57559 560/* cru_softrst_con4 */561#define SRST_A_PERIMID_NIU 64562#define SRST_H_PERIMID_NIU 65563#define SRST_A_GIC_AUDIO_NIU 66564#define SRST_H_GIC_AUDIO_NIU 67565#define SRST_A_GIC600 68566#define SRST_A_GIC600_DEBUG 69567#define SRST_A_GICADB_CORE2GIC 70568#define SRST_A_GICADB_GIC2CORE 71569#define SRST_A_SPINLOCK 72570#define SRST_H_SDMMC_BUFFER 73571#define SRST_D_SDMMC_BUFFER 74572#define SRST_H_I2S0_8CH 75573#define SRST_H_I2S1_8CH 76574#define SRST_H_I2S2_2CH 77575#define SRST_H_I2S3_2CH 78576 577/* cru_softrst_con5 */578#define SRST_M_I2S0_8CH_TX 80579#define SRST_M_I2S0_8CH_RX 81580#define SRST_M_I2S1_8CH_TX 82581#define SRST_M_I2S1_8CH_RX 83582#define SRST_M_I2S2_2CH 84583#define SRST_M_I2S3_2CH_TX 85584#define SRST_M_I2S3_2CH_RX 86585#define SRST_H_PDM 87586#define SRST_M_PDM 88587#define SRST_H_VAD 89588#define SRST_H_SPDIF_8CH 90589#define SRST_M_SPDIF_8CH 91590#define SRST_H_AUDPWM 92591#define SRST_S_AUDPWM 93592#define SRST_H_ACDCDIG 94593#define SRST_ACDCDIG 95594 595/* cru_softrst_con6 */596#define SRST_A_SECURE_FLASH_NIU 96597#define SRST_H_SECURE_FLASH_NIU 97598#define SRST_A_CRYPTO_NS 103599#define SRST_H_CRYPTO_NS 104600#define SRST_CRYPTO_NS_CORE 105601#define SRST_CRYPTO_NS_PKA 106602#define SRST_CRYPTO_NS_RNG 107603#define SRST_H_TRNG_NS 108604#define SRST_TRNG_NS 109605 606/* cru_softrst_con7 */607#define SRST_H_NANDC 112608#define SRST_N_NANDC 113609#define SRST_H_SFC 114610#define SRST_H_SFC_XIP 115611#define SRST_S_SFC 116612#define SRST_A_EMMC 117613#define SRST_H_EMMC 118614#define SRST_B_EMMC 119615#define SRST_C_EMMC 120616#define SRST_T_EMMC 121617 618/* cru_softrst_con8 */619#define SRST_A_PIPE_NIU 128620#define SRST_P_PIPE_NIU 130621#define SRST_P_PIPE_GRF 133622#define SRST_A_SATA0 134623#define SRST_SATA0_PIPE 135624#define SRST_SATA0_PMALIVE 136625#define SRST_SATA0_RXOOB 137626#define SRST_A_SATA1 138627#define SRST_SATA1_PIPE 139628#define SRST_SATA1_PMALIVE 140629#define SRST_SATA1_RXOOB 141630 631/* cru_softrst_con9 */632#define SRST_A_SATA2 144633#define SRST_SATA2_PIPE 145634#define SRST_SATA2_PMALIVE 146635#define SRST_SATA2_RXOOB 147636#define SRST_USB3OTG0 148637#define SRST_USB3OTG1 149638#define SRST_XPCS 150639#define SRST_XPCS_TX_DIV10 151640#define SRST_XPCS_RX_DIV10 152641#define SRST_XPCS_XGXS_RX 153642 643/* cru_softrst_con10 */644#define SRST_P_PCIE20 160645#define SRST_PCIE20_POWERUP 161646#define SRST_MSTR_ARESET_PCIE20 162647#define SRST_SLV_ARESET_PCIE20 163648#define SRST_DBI_ARESET_PCIE20 164649#define SRST_BRESET_PCIE20 165650#define SRST_PERST_PCIE20 166651#define SRST_CORE_RST_PCIE20 167652#define SRST_NSTICKY_RST_PCIE20 168653#define SRST_STICKY_RST_PCIE20 169654#define SRST_PWR_RST_PCIE20 170655 656/* cru_softrst_con11 */657#define SRST_P_PCIE30X1 176658#define SRST_PCIE30X1_POWERUP 177659#define SRST_M_ARESET_PCIE30X1 178660#define SRST_S_ARESET_PCIE30X1 179661#define SRST_D_ARESET_PCIE30X1 180662#define SRST_BRESET_PCIE30X1 181663#define SRST_PERST_PCIE30X1 182664#define SRST_CORE_RST_PCIE30X1 183665#define SRST_NSTC_RST_PCIE30X1 184666#define SRST_STC_RST_PCIE30X1 185667#define SRST_PWR_RST_PCIE30X1 186668 669/* cru_softrst_con12 */670#define SRST_P_PCIE30X2 192671#define SRST_PCIE30X2_POWERUP 193672#define SRST_M_ARESET_PCIE30X2 194673#define SRST_S_ARESET_PCIE30X2 195674#define SRST_D_ARESET_PCIE30X2 196675#define SRST_BRESET_PCIE30X2 197676#define SRST_PERST_PCIE30X2 198677#define SRST_CORE_RST_PCIE30X2 199678#define SRST_NSTC_RST_PCIE30X2 200679#define SRST_STC_RST_PCIE30X2 201680#define SRST_PWR_RST_PCIE30X2 202681 682/* cru_softrst_con13 */683#define SRST_A_PHP_NIU 208684#define SRST_H_PHP_NIU 209685#define SRST_P_PHP_NIU 210686#define SRST_H_SDMMC0 211687#define SRST_SDMMC0 212688#define SRST_H_SDMMC1 213689#define SRST_SDMMC1 214690#define SRST_A_GMAC0 215691#define SRST_GMAC0_TIMESTAMP 216692 693/* cru_softrst_con14 */694#define SRST_A_USB_NIU 224695#define SRST_H_USB_NIU 225696#define SRST_P_USB_NIU 226697#define SRST_P_USB_GRF 227698#define SRST_H_USB2HOST0 228699#define SRST_H_USB2HOST0_ARB 229700#define SRST_USB2HOST0_UTMI 230701#define SRST_H_USB2HOST1 231702#define SRST_H_USB2HOST1_ARB 232703#define SRST_USB2HOST1_UTMI 233704#define SRST_H_SDMMC2 234705#define SRST_SDMMC2 235706#define SRST_A_GMAC1 236707#define SRST_GMAC1_TIMESTAMP 237708 709/* cru_softrst_con15 */710#define SRST_A_VI_NIU 240711#define SRST_H_VI_NIU 241712#define SRST_P_VI_NIU 242713#define SRST_A_VICAP 247714#define SRST_H_VICAP 248715#define SRST_D_VICAP 249716#define SRST_I_VICAP 250717#define SRST_P_VICAP 251718#define SRST_H_ISP 252719#define SRST_ISP 253720#define SRST_P_CSI2HOST1 255721 722/* cru_softrst_con16 */723#define SRST_A_VO_NIU 256724#define SRST_H_VO_NIU 257725#define SRST_P_VO_NIU 258726#define SRST_A_VOP_NIU 259727#define SRST_A_VOP 260728#define SRST_H_VOP 261729#define SRST_VOP0 262730#define SRST_VOP1 263731#define SRST_VOP2 264732#define SRST_VOP_PWM 265733#define SRST_A_HDCP 266734#define SRST_H_HDCP 267735#define SRST_P_HDCP 268736#define SRST_P_HDMI_HOST 270737#define SRST_HDMI_HOST 271738 739/* cru_softrst_con17 */740#define SRST_P_DSITX_0 272741#define SRST_P_DSITX_1 273742#define SRST_P_EDP_CTRL 274743#define SRST_EDP_24M 275744#define SRST_A_VPU_NIU 280745#define SRST_H_VPU_NIU 281746#define SRST_A_VPU 282747#define SRST_H_VPU 283748#define SRST_H_EINK 286749#define SRST_P_EINK 287750 751/* cru_softrst_con18 */752#define SRST_A_RGA_NIU 288753#define SRST_H_RGA_NIU 289754#define SRST_P_RGA_NIU 290755#define SRST_A_RGA 292756#define SRST_H_RGA 293757#define SRST_RGA_CORE 294758#define SRST_A_IEP 295759#define SRST_H_IEP 296760#define SRST_IEP_CORE 297761#define SRST_H_EBC 298762#define SRST_D_EBC 299763#define SRST_A_JDEC 300764#define SRST_H_JDEC 301765#define SRST_A_JENC 302766#define SRST_H_JENC 303767 768/* cru_softrst_con19 */769#define SRST_A_VENC_NIU 304770#define SRST_H_VENC_NIU 305771#define SRST_A_RKVENC 307772#define SRST_H_RKVENC 308773#define SRST_RKVENC_CORE 309774 775/* cru_softrst_con20 */776#define SRST_A_RKVDEC_NIU 320777#define SRST_H_RKVDEC_NIU 321778#define SRST_A_RKVDEC 322779#define SRST_H_RKVDEC 323780#define SRST_RKVDEC_CA 324781#define SRST_RKVDEC_CORE 325782#define SRST_RKVDEC_HEVC_CA 326783 784/* cru_softrst_con21 */785#define SRST_A_BUS_NIU 336786#define SRST_P_BUS_NIU 338787#define SRST_P_CAN0 340788#define SRST_CAN0 341789#define SRST_P_CAN1 342790#define SRST_CAN1 343791#define SRST_P_CAN2 344792#define SRST_CAN2 345793#define SRST_P_GPIO1 346794#define SRST_GPIO1 347795#define SRST_P_GPIO2 348796#define SRST_GPIO2 349797#define SRST_P_GPIO3 350798#define SRST_GPIO3 351799 800/* cru_softrst_con22 */801#define SRST_P_GPIO4 352802#define SRST_GPIO4 353803#define SRST_P_I2C1 354804#define SRST_I2C1 355805#define SRST_P_I2C2 356806#define SRST_I2C2 357807#define SRST_P_I2C3 358808#define SRST_I2C3 359809#define SRST_P_I2C4 360810#define SRST_I2C4 361811#define SRST_P_I2C5 362812#define SRST_I2C5 363813#define SRST_P_OTPC_NS 364814#define SRST_OTPC_NS_SBPI 365815#define SRST_OTPC_NS_USR 366816 817/* cru_softrst_con23 */818#define SRST_P_PWM1 368819#define SRST_PWM1 369820#define SRST_P_PWM2 370821#define SRST_PWM2 371822#define SRST_P_PWM3 372823#define SRST_PWM3 373824#define SRST_P_SPI0 374825#define SRST_SPI0 375826#define SRST_P_SPI1 376827#define SRST_SPI1 377828#define SRST_P_SPI2 378829#define SRST_SPI2 379830#define SRST_P_SPI3 380831#define SRST_SPI3 381832 833/* cru_softrst_con24 */834#define SRST_P_SARADC 384835#define SRST_P_TSADC 385836#define SRST_TSADC 386837#define SRST_P_TIMER 387838#define SRST_TIMER0 388839#define SRST_TIMER1 389840#define SRST_TIMER2 390841#define SRST_TIMER3 391842#define SRST_TIMER4 392843#define SRST_TIMER5 393844#define SRST_P_UART1 394845#define SRST_S_UART1 395846 847/* cru_softrst_con25 */848#define SRST_P_UART2 400849#define SRST_S_UART2 401850#define SRST_P_UART3 402851#define SRST_S_UART3 403852#define SRST_P_UART4 404853#define SRST_S_UART4 405854#define SRST_P_UART5 406855#define SRST_S_UART5 407856#define SRST_P_UART6 408857#define SRST_S_UART6 409858#define SRST_P_UART7 410859#define SRST_S_UART7 411860#define SRST_P_UART8 412861#define SRST_S_UART8 413862#define SRST_P_UART9 414863#define SRST_S_UART9 415864 865/* cru_softrst_con26 */866#define SRST_P_GRF 416867#define SRST_P_GRF_VCCIO12 417868#define SRST_P_GRF_VCCIO34 418869#define SRST_P_GRF_VCCIO567 419870#define SRST_P_SCR 420871#define SRST_P_WDT_NS 421872#define SRST_T_WDT_NS 422873#define SRST_P_DFT2APB 423874#define SRST_A_MCU 426875#define SRST_P_INTMUX 427876#define SRST_P_MAILBOX 428877 878/* cru_softrst_con27 */879#define SRST_A_TOP_HIGH_NIU 432880#define SRST_A_TOP_LOW_NIU 433881#define SRST_H_TOP_NIU 434882#define SRST_P_TOP_NIU 435883#define SRST_P_TOP_CRU 438884#define SRST_P_DDRPHY 439885#define SRST_DDRPHY 440886#define SRST_P_MIPICSIPHY 442887#define SRST_P_MIPIDSIPHY0 443888#define SRST_P_MIPIDSIPHY1 444889#define SRST_P_PCIE30PHY 445890#define SRST_PCIE30PHY 446891#define SRST_P_PCIE30PHY_GRF 447892 893/* cru_softrst_con28 */894#define SRST_P_APB2ASB_LEFT 448895#define SRST_P_APB2ASB_BOTTOM 449896#define SRST_P_ASB2APB_LEFT 450897#define SRST_P_ASB2APB_BOTTOM 451898#define SRST_P_PIPEPHY0 452899#define SRST_PIPEPHY0 453900#define SRST_P_PIPEPHY1 454901#define SRST_PIPEPHY1 455902#define SRST_P_PIPEPHY2 456903#define SRST_PIPEPHY2 457904#define SRST_P_USB2PHY0_GRF 458905#define SRST_P_USB2PHY1_GRF 459906#define SRST_P_CPU_BOOST 460907#define SRST_CPU_BOOST 461908#define SRST_P_OTPPHY 462909#define SRST_OTPPHY 463910 911/* cru_softrst_con29 */912#define SRST_USB2PHY0_POR 464913#define SRST_USB2PHY0_USB3OTG0 465914#define SRST_USB2PHY0_USB3OTG1 466915#define SRST_USB2PHY1_POR 467916#define SRST_USB2PHY1_USB2HOST0 468917#define SRST_USB2PHY1_USB2HOST1 469918#define SRST_P_EDPPHY_GRF 470919#define SRST_TSADCPHY 471920#define SRST_GMAC0_DELAYLINE 472921#define SRST_GMAC1_DELAYLINE 473922#define SRST_OTPC_ARB 474923#define SRST_P_PIPEPHY0_GRF 475924#define SRST_P_PIPEPHY1_GRF 476925#define SRST_P_PIPEPHY2_GRF 477926 927#endif928