593 lines · c
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */2/*3 * Copyright (c) 2023 Rockchip Electronics Co. Ltd.4 * Copyright (c) 2024 Collabora Ltd.5 *6 * Author: Elaine Zhang <zhangqing@rock-chips.com>7 * Author: Detlev Casanova <detlev.casanova@collabora.com>8 */9 10#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H11#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H12 13/* cru-clocks indices */14 15/* cru plls */16#define PLL_BPLL 017#define PLL_LPLL 118#define PLL_VPLL 219#define PLL_AUPLL 320#define PLL_CPLL 421#define PLL_GPLL 522#define PLL_PPLL 623#define ARMCLK_L 724#define ARMCLK_B 825 26/* cru clocks */27#define CLK_CPLL_DIV20 928#define CLK_CPLL_DIV10 1029#define CLK_GPLL_DIV8 1130#define CLK_GPLL_DIV6 1231#define CLK_CPLL_DIV4 1332#define CLK_GPLL_DIV4 1433#define CLK_SPLL_DIV2 1534#define CLK_GPLL_DIV3 1635#define CLK_CPLL_DIV2 1736#define CLK_GPLL_DIV2 1837#define CLK_SPLL_DIV1 1938#define PCLK_TOP_ROOT 2039#define ACLK_TOP 2140#define HCLK_TOP 2241#define CLK_AUDIO_FRAC_0 2342#define CLK_AUDIO_FRAC_1 2443#define CLK_AUDIO_FRAC_2 2544#define CLK_AUDIO_FRAC_3 2645#define CLK_UART_FRAC_0 2746#define CLK_UART_FRAC_1 2847#define CLK_UART_FRAC_2 2948#define CLK_UART1_SRC_TOP 3049#define CLK_AUDIO_INT_0 3150#define CLK_AUDIO_INT_1 3251#define CLK_AUDIO_INT_2 3352#define CLK_PDM0_SRC_TOP 3453#define CLK_PDM1_OUT 3554#define CLK_GMAC0_125M_SRC 3655#define CLK_GMAC1_125M_SRC 3756#define LCLK_ASRC_SRC_0 3857#define LCLK_ASRC_SRC_1 3958#define REF_CLK0_OUT_PLL 4059#define REF_CLK1_OUT_PLL 4160#define REF_CLK2_OUT_PLL 4261#define REFCLKO25M_GMAC0_OUT 4362#define REFCLKO25M_GMAC1_OUT 4463#define CLK_CIFOUT_OUT 4564#define CLK_GMAC0_RMII_CRU 4665#define CLK_GMAC1_RMII_CRU 4766#define CLK_OTPC_AUTO_RD_G 4867#define CLK_OTP_PHY_G 4968#define CLK_MIPI_CAMERAOUT_M0 5069#define CLK_MIPI_CAMERAOUT_M1 5170#define CLK_MIPI_CAMERAOUT_M2 5271#define MCLK_PDM0_SRC_TOP 5372#define HCLK_AUDIO_ROOT 5473#define HCLK_ASRC_2CH_0 5574#define HCLK_ASRC_2CH_1 5675#define HCLK_ASRC_4CH_0 5776#define HCLK_ASRC_4CH_1 5877#define CLK_ASRC_2CH_0 5978#define CLK_ASRC_2CH_1 6079#define CLK_ASRC_4CH_0 6180#define CLK_ASRC_4CH_1 6281#define MCLK_SAI0_8CH_SRC 6382#define MCLK_SAI0_8CH 6483#define HCLK_SAI0_8CH 6584#define HCLK_SPDIF_RX0 6685#define MCLK_SPDIF_RX0 6786#define HCLK_SPDIF_RX1 6887#define MCLK_SPDIF_RX1 6988#define MCLK_SAI1_8CH_SRC 7089#define MCLK_SAI1_8CH 7190#define HCLK_SAI1_8CH 7291#define MCLK_SAI2_2CH_SRC 7392#define MCLK_SAI2_2CH 7493#define HCLK_SAI2_2CH 7594#define MCLK_SAI3_2CH_SRC 7695#define MCLK_SAI3_2CH 7796#define HCLK_SAI3_2CH 7897#define MCLK_SAI4_2CH_SRC 7998#define MCLK_SAI4_2CH 8099#define HCLK_SAI4_2CH 81100#define HCLK_ACDCDIG_DSM 82101#define MCLK_ACDCDIG_DSM 83102#define CLK_PDM1 84103#define HCLK_PDM1 85104#define MCLK_PDM1 86105#define HCLK_SPDIF_TX0 87106#define MCLK_SPDIF_TX0 88107#define HCLK_SPDIF_TX1 89108#define MCLK_SPDIF_TX1 90109#define CLK_SAI1_MCLKOUT 91110#define CLK_SAI2_MCLKOUT 92111#define CLK_SAI3_MCLKOUT 93112#define CLK_SAI4_MCLKOUT 94113#define CLK_SAI0_MCLKOUT 95114#define HCLK_BUS_ROOT 96115#define PCLK_BUS_ROOT 97116#define ACLK_BUS_ROOT 98117#define HCLK_CAN0 99118#define CLK_CAN0 100119#define HCLK_CAN1 101120#define CLK_CAN1 102121#define CLK_KEY_SHIFT 103122#define PCLK_I2C1 104123#define PCLK_I2C2 105124#define PCLK_I2C3 106125#define PCLK_I2C4 107126#define PCLK_I2C5 108127#define PCLK_I2C6 109128#define PCLK_I2C7 110129#define PCLK_I2C8 111130#define PCLK_I2C9 112131#define PCLK_WDT_BUSMCU 113132#define TCLK_WDT_BUSMCU 114133#define ACLK_GIC 115134#define CLK_I2C1 116135#define CLK_I2C2 117136#define CLK_I2C3 118137#define CLK_I2C4 119138#define CLK_I2C5 120139#define CLK_I2C6 121140#define CLK_I2C7 122141#define CLK_I2C8 123142#define CLK_I2C9 124143#define PCLK_SARADC 125144#define CLK_SARADC 126145#define PCLK_TSADC 127146#define CLK_TSADC 128147#define PCLK_UART0 129148#define PCLK_UART2 130149#define PCLK_UART3 131150#define PCLK_UART4 132151#define PCLK_UART5 133152#define PCLK_UART6 134153#define PCLK_UART7 135154#define PCLK_UART8 136155#define PCLK_UART9 137156#define PCLK_UART10 138157#define PCLK_UART11 139158#define SCLK_UART0 140159#define SCLK_UART2 141160#define SCLK_UART3 142161#define SCLK_UART4 143162#define SCLK_UART5 144163#define SCLK_UART6 145164#define SCLK_UART7 146165#define SCLK_UART8 147166#define SCLK_UART9 148167#define SCLK_UART10 149168#define SCLK_UART11 150169#define PCLK_SPI0 151170#define PCLK_SPI1 152171#define PCLK_SPI2 153172#define PCLK_SPI3 154173#define PCLK_SPI4 155174#define CLK_SPI0 156175#define CLK_SPI1 157176#define CLK_SPI2 158177#define CLK_SPI3 159178#define CLK_SPI4 160179#define PCLK_WDT0 161180#define TCLK_WDT0 162181#define PCLK_PWM1 163182#define CLK_PWM1 164183#define CLK_OSC_PWM1 165184#define CLK_RC_PWM1 166185#define PCLK_BUSTIMER0 167186#define PCLK_BUSTIMER1 168187#define CLK_TIMER0_ROOT 169188#define CLK_TIMER0 170189#define CLK_TIMER1 171190#define CLK_TIMER2 172191#define CLK_TIMER3 173192#define CLK_TIMER4 174193#define CLK_TIMER5 175194#define PCLK_MAILBOX0 176195#define PCLK_GPIO1 177196#define DBCLK_GPIO1 178197#define PCLK_GPIO2 179198#define DBCLK_GPIO2 180199#define PCLK_GPIO3 181200#define DBCLK_GPIO3 182201#define PCLK_GPIO4 183202#define DBCLK_GPIO4 184203#define ACLK_DECOM 185204#define PCLK_DECOM 186205#define DCLK_DECOM 187206#define CLK_TIMER1_ROOT 188207#define CLK_TIMER6 189208#define CLK_TIMER7 190209#define CLK_TIMER8 191210#define CLK_TIMER9 192211#define CLK_TIMER10 193212#define CLK_TIMER11 194213#define ACLK_DMAC0 195214#define ACLK_DMAC1 196215#define ACLK_DMAC2 197216#define ACLK_SPINLOCK 198217#define HCLK_I3C0 199218#define HCLK_I3C1 200219#define HCLK_BUS_CM0_ROOT 201220#define FCLK_BUS_CM0_CORE 202221#define CLK_BUS_CM0_RTC 203222#define PCLK_PMU2 204223#define PCLK_PWM2 205224#define CLK_PWM2 206225#define CLK_RC_PWM2 207226#define CLK_OSC_PWM2 208227#define CLK_FREQ_PWM1 209228#define CLK_COUNTER_PWM1 210229#define SAI_SCLKIN_FREQ 211230#define SAI_SCLKIN_COUNTER 212231#define CLK_I3C0 213232#define CLK_I3C1 214233#define PCLK_CSIDPHY1 215234#define PCLK_DDR_ROOT 216235#define PCLK_DDR_MON_CH0 217236#define TMCLK_DDR_MON_CH0 218237#define ACLK_DDR_ROOT 219238#define HCLK_DDR_ROOT 220239#define FCLK_DDR_CM0_CORE 221240#define CLK_DDR_TIMER_ROOT 222241#define CLK_DDR_TIMER0 223242#define CLK_DDR_TIMER1 224243#define TCLK_WDT_DDR 225244#define PCLK_WDT 226245#define PCLK_TIMER 227246#define CLK_DDR_CM0_RTC 228247#define ACLK_RKNN0 229248#define ACLK_RKNN1 230249#define HCLK_RKNN_ROOT 231250#define CLK_RKNN_DSU0 232251#define PCLK_NPUTOP_ROOT 233252#define PCLK_NPU_TIMER 234253#define CLK_NPUTIMER_ROOT 235254#define CLK_NPUTIMER0 236255#define CLK_NPUTIMER1 237256#define PCLK_NPU_WDT 238257#define TCLK_NPU_WDT 239258#define ACLK_RKNN_CBUF 240259#define HCLK_NPU_CM0_ROOT 241260#define FCLK_NPU_CM0_CORE 242261#define CLK_NPU_CM0_RTC 243262#define HCLK_RKNN_CBUF 244263#define HCLK_NVM_ROOT 245264#define ACLK_NVM_ROOT 246265#define SCLK_FSPI_X2 247266#define HCLK_FSPI 248267#define CCLK_SRC_EMMC 249268#define HCLK_EMMC 250269#define ACLK_EMMC 251270#define BCLK_EMMC 252271#define TCLK_EMMC 253272#define PCLK_PHP_ROOT 254273#define ACLK_PHP_ROOT 255274#define PCLK_PCIE0 256275#define CLK_PCIE0_AUX 257276#define ACLK_PCIE0_MST 258277#define ACLK_PCIE0_SLV 259278#define ACLK_PCIE0_DBI 260279#define ACLK_USB3OTG1 261280#define CLK_REF_USB3OTG1 262281#define CLK_SUSPEND_USB3OTG1 263282#define ACLK_MMU0 264283#define ACLK_SLV_MMU0 265284#define ACLK_MMU1 266285#define ACLK_SLV_MMU1 267286#define PCLK_PCIE1 268287#define CLK_PCIE1_AUX 269288#define ACLK_PCIE1_MST 270289#define ACLK_PCIE1_SLV 271290#define ACLK_PCIE1_DBI 272291#define CLK_RXOOB0 273292#define CLK_RXOOB1 274293#define CLK_PMALIVE0 275294#define CLK_PMALIVE1 276295#define ACLK_SATA0 277296#define ACLK_SATA1 278297#define CLK_USB3OTG1_PIPE_PCLK 279298#define CLK_USB3OTG1_UTMI 280299#define CLK_USB3OTG0_PIPE_PCLK 281300#define CLK_USB3OTG0_UTMI 282301#define HCLK_SDGMAC_ROOT 283302#define ACLK_SDGMAC_ROOT 284303#define PCLK_SDGMAC_ROOT 285304#define ACLK_GMAC0 286305#define ACLK_GMAC1 287306#define PCLK_GMAC0 288307#define PCLK_GMAC1 289308#define CCLK_SRC_SDIO 290309#define HCLK_SDIO 291310#define CLK_GMAC1_PTP_REF 292311#define CLK_GMAC0_PTP_REF 293312#define CLK_GMAC1_PTP_REF_SRC 294313#define CLK_GMAC0_PTP_REF_SRC 295314#define CCLK_SRC_SDMMC0 296315#define HCLK_SDMMC0 297316#define SCLK_FSPI1_X2 298317#define HCLK_FSPI1 299318#define ACLK_DSMC_ROOT 300319#define ACLK_DSMC 301320#define PCLK_DSMC 302321#define CLK_DSMC_SYS 303322#define HCLK_HSGPIO 304323#define CLK_HSGPIO_TX 305324#define CLK_HSGPIO_RX 306325#define ACLK_HSGPIO 307326#define PCLK_PHPPHY_ROOT 308327#define PCLK_PCIE2_COMBOPHY0 309328#define PCLK_PCIE2_COMBOPHY1 310329#define CLK_PCIE_100M_SRC 311330#define CLK_PCIE_100M_NDUTY_SRC 312331#define CLK_REF_PCIE0_PHY 313332#define CLK_REF_PCIE1_PHY 314333#define CLK_REF_MPHY_26M 315334#define HCLK_RKVDEC_ROOT 316335#define ACLK_RKVDEC_ROOT 317336#define HCLK_RKVDEC 318337#define CLK_RKVDEC_HEVC_CA 319338#define CLK_RKVDEC_CORE 320339#define ACLK_UFS_ROOT 321340#define ACLK_USB_ROOT 322341#define PCLK_USB_ROOT 323342#define ACLK_USB3OTG0 324343#define CLK_REF_USB3OTG0 325344#define CLK_SUSPEND_USB3OTG0 326345#define ACLK_MMU2 327346#define ACLK_SLV_MMU2 328347#define ACLK_UFS_SYS 329348#define ACLK_VPU_ROOT 330349#define ACLK_VPU_MID_ROOT 331350#define HCLK_VPU_ROOT 332351#define ACLK_JPEG_ROOT 333352#define ACLK_VPU_LOW_ROOT 334353#define HCLK_RGA2E_0 335354#define ACLK_RGA2E_0 336355#define CLK_CORE_RGA2E_0 337356#define ACLK_JPEG 338357#define HCLK_JPEG 339358#define HCLK_VDPP 340359#define ACLK_VDPP 341360#define CLK_CORE_VDPP 342361#define HCLK_RGA2E_1 343362#define ACLK_RGA2E_1 344363#define CLK_CORE_RGA2E_1 345364#define DCLK_EBC_FRAC_SRC 346365#define HCLK_EBC 347366#define ACLK_EBC 348367#define DCLK_EBC 349368#define HCLK_VEPU0_ROOT 350369#define ACLK_VEPU0_ROOT 351370#define HCLK_VEPU0 352371#define ACLK_VEPU0 353372#define CLK_VEPU0_CORE 354373#define ACLK_VI_ROOT 355374#define HCLK_VI_ROOT 356375#define PCLK_VI_ROOT 357376#define DCLK_VICAP 358377#define ACLK_VICAP 359378#define HCLK_VICAP 360379#define CLK_ISP_CORE 361380#define CLK_ISP_CORE_MARVIN 362381#define CLK_ISP_CORE_VICAP 363382#define ACLK_ISP 364383#define HCLK_ISP 365384#define ACLK_VPSS 366385#define HCLK_VPSS 367386#define CLK_CORE_VPSS 368387#define PCLK_CSI_HOST_0 369388#define PCLK_CSI_HOST_1 370389#define PCLK_CSI_HOST_2 371390#define PCLK_CSI_HOST_3 372391#define PCLK_CSI_HOST_4 373392#define ICLK_CSIHOST01 374393#define ICLK_CSIHOST0 375394#define CLK_ISP_PVTPLL_SRC 376395#define ACLK_VI_ROOT_INTER 377396#define CLK_VICAP_I0CLK 378397#define CLK_VICAP_I1CLK 379398#define CLK_VICAP_I2CLK 380399#define CLK_VICAP_I3CLK 381400#define CLK_VICAP_I4CLK 382401#define ACLK_VOP_ROOT 383402#define HCLK_VOP_ROOT 384403#define PCLK_VOP_ROOT 385404#define HCLK_VOP 386405#define ACLK_VOP 387406#define DCLK_VP0_SRC 388407#define DCLK_VP1_SRC 389408#define DCLK_VP2_SRC 390409#define DCLK_VP0 391410#define DCLK_VP1 392411#define DCLK_VP2 393412#define PCLK_VOPGRF 394413#define ACLK_VO0_ROOT 395414#define HCLK_VO0_ROOT 396415#define PCLK_VO0_ROOT 397416#define PCLK_VO0_GRF 398417#define ACLK_HDCP0 399418#define HCLK_HDCP0 400419#define PCLK_HDCP0 401420#define CLK_TRNG0_SKP 402421#define PCLK_DSIHOST0 403422#define CLK_DSIHOST0 404423#define PCLK_HDMITX0 405424#define CLK_HDMITX0_EARC 406425#define CLK_HDMITX0_REF 407426#define PCLK_EDP0 408427#define CLK_EDP0_24M 409428#define CLK_EDP0_200M 410429#define MCLK_SAI5_8CH_SRC 411430#define MCLK_SAI5_8CH 412431#define HCLK_SAI5_8CH 413432#define MCLK_SAI6_8CH_SRC 414433#define MCLK_SAI6_8CH 415434#define HCLK_SAI6_8CH 416435#define HCLK_SPDIF_TX2 417436#define MCLK_SPDIF_TX2 418437#define HCLK_SPDIF_RX2 419438#define MCLK_SPDIF_RX2 420439#define HCLK_SAI8_8CH 421440#define MCLK_SAI8_8CH_SRC 422441#define MCLK_SAI8_8CH 423442#define ACLK_VO1_ROOT 424443#define HCLK_VO1_ROOT 425444#define PCLK_VO1_ROOT 426445#define MCLK_SAI7_8CH_SRC 427446#define MCLK_SAI7_8CH 428447#define HCLK_SAI7_8CH 429448#define HCLK_SPDIF_TX3 430449#define HCLK_SPDIF_TX4 431450#define HCLK_SPDIF_TX5 432451#define MCLK_SPDIF_TX3 433452#define CLK_AUX16MHZ_0 434453#define ACLK_DP0 435454#define PCLK_DP0 436455#define PCLK_VO1_GRF 437456#define ACLK_HDCP1 438457#define HCLK_HDCP1 439458#define PCLK_HDCP1 440459#define CLK_TRNG1_SKP 441460#define HCLK_SAI9_8CH 442461#define MCLK_SAI9_8CH_SRC 443462#define MCLK_SAI9_8CH 444463#define MCLK_SPDIF_TX4 445464#define MCLK_SPDIF_TX5 446465#define CLK_GPU_SRC_PRE 447466#define CLK_GPU 448467#define PCLK_GPU_ROOT 449468#define ACLK_CENTER_ROOT 450469#define ACLK_CENTER_LOW_ROOT 451470#define HCLK_CENTER_ROOT 452471#define PCLK_CENTER_ROOT 453472#define ACLK_DMA2DDR 454473#define ACLK_DDR_SHAREMEM 455474#define PCLK_DMA2DDR 456475#define PCLK_SHAREMEM 457476#define HCLK_VEPU1_ROOT 458477#define ACLK_VEPU1_ROOT 459478#define HCLK_VEPU1 460479#define ACLK_VEPU1 461480#define CLK_VEPU1_CORE 462481#define CLK_JDBCK_DAP 463482#define PCLK_MIPI_DCPHY 464483#define CLK_32K_USB2DEBUG 465484#define PCLK_CSIDPHY 466485#define PCLK_USBDPPHY 467486#define CLK_PMUPHY_REF_SRC 468487#define CLK_USBDP_COMBO_PHY_IMMORTAL 469488#define CLK_HDMITXHDP 470489#define PCLK_MPHY 471490#define CLK_REF_OSC_MPHY 472491#define CLK_REF_UFS_CLKOUT 473492#define HCLK_PMU1_ROOT 474493#define HCLK_PMU_CM0_ROOT 475494#define CLK_200M_PMU_SRC 476495#define CLK_100M_PMU_SRC 477496#define CLK_50M_PMU_SRC 478497#define FCLK_PMU_CM0_CORE 479498#define CLK_PMU_CM0_RTC 480499#define PCLK_PMU1 481500#define CLK_PMU1 482501#define PCLK_PMU1WDT 483502#define TCLK_PMU1WDT 484503#define PCLK_PMUTIMER 485504#define CLK_PMUTIMER_ROOT 486505#define CLK_PMUTIMER0 487506#define CLK_PMUTIMER1 488507#define PCLK_PMU1PWM 489508#define CLK_PMU1PWM 490509#define CLK_PMU1PWM_OSC 491510#define PCLK_PMUPHY_ROOT 492511#define PCLK_I2C0 493512#define CLK_I2C0 494513#define SCLK_UART1 495514#define PCLK_UART1 496515#define CLK_PMU1PWM_RC 497516#define CLK_PDM0 498517#define HCLK_PDM0 499518#define MCLK_PDM0 500519#define HCLK_VAD 501520#define CLK_OSCCHK_PVTM 502521#define CLK_PDM0_OUT 503522#define CLK_HPTIMER_SRC 504523#define PCLK_PMU0_ROOT 505524#define PCLK_PMU0 506525#define PCLK_GPIO0 507526#define DBCLK_GPIO0 508527#define CLK_OSC0_PMU1 509528#define PCLK_PMU1_ROOT 510529#define XIN_OSC0_DIV 511530#define ACLK_USB 512531#define ACLK_UFS 513532#define ACLK_SDGMAC 514533#define HCLK_SDGMAC 515534#define PCLK_SDGMAC 516535#define HCLK_VO1 517536#define HCLK_VO0 518537#define PCLK_CCI_ROOT 519538#define ACLK_CCI_ROOT 520539#define HCLK_VO0VOP_CHANNEL 521540#define ACLK_VO0VOP_CHANNEL 522541#define ACLK_TOP_MID 523542#define ACLK_SECURE_HIGH 524543#define CLK_USBPHY_REF_SRC 525544#define CLK_PHY_REF_SRC 526545#define CLK_CPLL_REF_SRC 527546#define CLK_AUPLL_REF_SRC 528547#define PCLK_SECURE_NS 529548#define HCLK_SECURE_NS 530549#define ACLK_SECURE_NS 531550#define PCLK_OTPC_NS 532551#define HCLK_CRYPTO_NS 533552#define HCLK_TRNG_NS 534553#define CLK_OTPC_NS 535554#define SCLK_DSU 536555#define SCLK_DDR 537556#define ACLK_CRYPTO_NS 538557#define CLK_PKA_CRYPTO_NS 539558#define ACLK_RKVDEC_ROOT_BAK 540559#define CLK_AUDIO_FRAC_0_SRC 541560#define CLK_AUDIO_FRAC_1_SRC 542561#define CLK_AUDIO_FRAC_2_SRC 543562#define CLK_AUDIO_FRAC_3_SRC 544563#define PCLK_HDPTX_APB 545564 565/* secure clk */566#define CLK_STIMER0_ROOT 546567#define CLK_STIMER1_ROOT 547568#define PCLK_SECURE_S 548569#define HCLK_SECURE_S 549570#define ACLK_SECURE_S 550571#define CLK_PKA_CRYPTO_S 551572#define HCLK_VO1_S 552573#define PCLK_VO1_S 553574#define HCLK_VO0_S 554575#define PCLK_VO0_S 555576#define PCLK_KLAD 556577#define HCLK_CRYPTO_S 557578#define HCLK_KLAD 558579#define ACLK_CRYPTO_S 559580#define HCLK_TRNG_S 560581#define PCLK_OTPC_S 561582#define CLK_OTPC_S 562583#define PCLK_WDT_S 563584#define TCLK_WDT_S 564585#define PCLK_HDCP0_TRNG 565586#define PCLK_HDCP1_TRNG 566587#define HCLK_HDCP_KEY0 567588#define HCLK_HDCP_KEY1 568589#define PCLK_EDP_S 569590#define ACLK_KLAD 570591 592#endif593