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1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */2/*3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.4 * Copyright (c) 2022 Collabora Ltd.5 *6 * Author: Elaine Zhang <zhangqing@rock-chips.com>7 * Author: Sebastian Reichel <sebastian.reichel@collabora.com>8 */9 10#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H11#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H12 13/* cru-clocks indices */14 15#define PLL_B0PLL 016#define PLL_B1PLL 117#define PLL_LPLL 218#define PLL_V0PLL 319#define PLL_AUPLL 420#define PLL_CPLL 521#define PLL_GPLL 622#define PLL_NPLL 723#define PLL_PPLL 824#define ARMCLK_L 925#define ARMCLK_B01 1026#define ARMCLK_B23 1127#define PCLK_BIGCORE0_ROOT 1228#define PCLK_BIGCORE0_PVTM 1329#define PCLK_BIGCORE1_ROOT 1430#define PCLK_BIGCORE1_PVTM 1531#define PCLK_DSU_S_ROOT 1632#define PCLK_DSU_ROOT 1733#define PCLK_DSU_NS_ROOT 1834#define PCLK_LITCORE_PVTM 1935#define PCLK_DBG 2036#define PCLK_DSU 2137#define PCLK_S_DAPLITE 2238#define PCLK_M_DAPLITE 2339#define MBIST_MCLK_PDM1 2440#define MBIST_CLK_ACDCDIG 2541#define HCLK_I2S2_2CH 2642#define HCLK_I2S3_2CH 2743#define CLK_I2S2_2CH_SRC 2844#define CLK_I2S2_2CH_FRAC 2945#define CLK_I2S2_2CH 3046#define MCLK_I2S2_2CH 3147#define I2S2_2CH_MCLKOUT 3248#define CLK_DAC_ACDCDIG 3349#define CLK_I2S3_2CH_SRC 3450#define CLK_I2S3_2CH_FRAC 3551#define CLK_I2S3_2CH 3652#define MCLK_I2S3_2CH 3753#define I2S3_2CH_MCLKOUT 3854#define PCLK_ACDCDIG 3955#define HCLK_I2S0_8CH 4056#define CLK_I2S0_8CH_TX_SRC 4157#define CLK_I2S0_8CH_TX_FRAC 4258#define MCLK_I2S0_8CH_TX 4359#define CLK_I2S0_8CH_TX 4460#define CLK_I2S0_8CH_RX_SRC 4561#define CLK_I2S0_8CH_RX_FRAC 4662#define MCLK_I2S0_8CH_RX 4763#define CLK_I2S0_8CH_RX 4864#define I2S0_8CH_MCLKOUT 4965#define HCLK_PDM1 5066#define MCLK_PDM1 5167#define HCLK_AUDIO_ROOT 5268#define PCLK_AUDIO_ROOT 5369#define HCLK_SPDIF0 5470#define CLK_SPDIF0_SRC 5571#define CLK_SPDIF0_FRAC 5672#define MCLK_SPDIF0 5773#define CLK_SPDIF0 5874#define CLK_SPDIF1 5975#define HCLK_SPDIF1 6076#define CLK_SPDIF1_SRC 6177#define CLK_SPDIF1_FRAC 6278#define MCLK_SPDIF1 6379#define ACLK_AV1_ROOT 6480#define ACLK_AV1 6581#define PCLK_AV1_ROOT 6682#define PCLK_AV1 6783#define PCLK_MAILBOX0 6884#define PCLK_MAILBOX1 6985#define PCLK_MAILBOX2 7086#define PCLK_PMU2 7187#define PCLK_PMUCM0_INTMUX 7288#define PCLK_DDRCM0_INTMUX 7389#define PCLK_TOP 7490#define PCLK_PWM1 7591#define CLK_PWM1 7692#define CLK_PWM1_CAPTURE 7793#define PCLK_PWM2 7894#define CLK_PWM2 7995#define CLK_PWM2_CAPTURE 8096#define PCLK_PWM3 8197#define CLK_PWM3 8298#define CLK_PWM3_CAPTURE 8399#define PCLK_BUSTIMER0 84100#define PCLK_BUSTIMER1 85101#define CLK_BUS_TIMER_ROOT 86102#define CLK_BUSTIMER0 87103#define CLK_BUSTIMER1 88104#define CLK_BUSTIMER2 89105#define CLK_BUSTIMER3 90106#define CLK_BUSTIMER4 91107#define CLK_BUSTIMER5 92108#define CLK_BUSTIMER6 93109#define CLK_BUSTIMER7 94110#define CLK_BUSTIMER8 95111#define CLK_BUSTIMER9 96112#define CLK_BUSTIMER10 97113#define CLK_BUSTIMER11 98114#define PCLK_WDT0 99115#define TCLK_WDT0 100116#define PCLK_CAN0 101117#define CLK_CAN0 102118#define PCLK_CAN1 103119#define CLK_CAN1 104120#define PCLK_CAN2 105121#define CLK_CAN2 106122#define ACLK_DECOM 107123#define PCLK_DECOM 108124#define DCLK_DECOM 109125#define ACLK_DMAC0 110126#define ACLK_DMAC1 111127#define ACLK_DMAC2 112128#define ACLK_BUS_ROOT 113129#define ACLK_GIC 114130#define PCLK_GPIO1 115131#define DBCLK_GPIO1 116132#define PCLK_GPIO2 117133#define DBCLK_GPIO2 118134#define PCLK_GPIO3 119135#define DBCLK_GPIO3 120136#define PCLK_GPIO4 121137#define DBCLK_GPIO4 122138#define PCLK_I2C1 123139#define PCLK_I2C2 124140#define PCLK_I2C3 125141#define PCLK_I2C4 126142#define PCLK_I2C5 127143#define PCLK_I2C6 128144#define PCLK_I2C7 129145#define PCLK_I2C8 130146#define CLK_I2C1 131147#define CLK_I2C2 132148#define CLK_I2C3 133149#define CLK_I2C4 134150#define CLK_I2C5 135151#define CLK_I2C6 136152#define CLK_I2C7 137153#define CLK_I2C8 138154#define PCLK_OTPC_NS 139155#define CLK_OTPC_NS 140156#define CLK_OTPC_ARB 141157#define CLK_OTPC_AUTO_RD_G 142158#define CLK_OTP_PHY_G 143159#define PCLK_SARADC 144160#define CLK_SARADC 145161#define PCLK_SPI0 146162#define PCLK_SPI1 147163#define PCLK_SPI2 148164#define PCLK_SPI3 149165#define PCLK_SPI4 150166#define CLK_SPI0 151167#define CLK_SPI1 152168#define CLK_SPI2 153169#define CLK_SPI3 154170#define CLK_SPI4 155171#define ACLK_SPINLOCK 156172#define PCLK_TSADC 157173#define CLK_TSADC 158174#define PCLK_UART1 159175#define PCLK_UART2 160176#define PCLK_UART3 161177#define PCLK_UART4 162178#define PCLK_UART5 163179#define PCLK_UART6 164180#define PCLK_UART7 165181#define PCLK_UART8 166182#define PCLK_UART9 167183#define CLK_UART1_SRC 168184#define CLK_UART1_FRAC 169185#define CLK_UART1 170186#define SCLK_UART1 171187#define CLK_UART2_SRC 172188#define CLK_UART2_FRAC 173189#define CLK_UART2 174190#define SCLK_UART2 175191#define CLK_UART3_SRC 176192#define CLK_UART3_FRAC 177193#define CLK_UART3 178194#define SCLK_UART3 179195#define CLK_UART4_SRC 180196#define CLK_UART4_FRAC 181197#define CLK_UART4 182198#define SCLK_UART4 183199#define CLK_UART5_SRC 184200#define CLK_UART5_FRAC 185201#define CLK_UART5 186202#define SCLK_UART5 187203#define CLK_UART6_SRC 188204#define CLK_UART6_FRAC 189205#define CLK_UART6 190206#define SCLK_UART6 191207#define CLK_UART7_SRC 192208#define CLK_UART7_FRAC 193209#define CLK_UART7 194210#define SCLK_UART7 195211#define CLK_UART8_SRC 196212#define CLK_UART8_FRAC 197213#define CLK_UART8 198214#define SCLK_UART8 199215#define CLK_UART9_SRC 200216#define CLK_UART9_FRAC 201217#define CLK_UART9 202218#define SCLK_UART9 203219#define ACLK_CENTER_ROOT 204220#define ACLK_CENTER_LOW_ROOT 205221#define HCLK_CENTER_ROOT 206222#define PCLK_CENTER_ROOT 207223#define ACLK_DMA2DDR 208224#define ACLK_DDR_SHAREMEM 209225#define ACLK_CENTER_S200_ROOT 210226#define ACLK_CENTER_S400_ROOT 211227#define FCLK_DDR_CM0_CORE 212228#define CLK_DDR_TIMER_ROOT 213229#define CLK_DDR_TIMER0 214230#define CLK_DDR_TIMER1 215231#define TCLK_WDT_DDR 216232#define CLK_DDR_CM0_RTC 217233#define PCLK_WDT 218234#define PCLK_TIMER 219235#define PCLK_DMA2DDR 220236#define PCLK_SHAREMEM 221237#define CLK_50M_SRC 222238#define CLK_100M_SRC 223239#define CLK_150M_SRC 224240#define CLK_200M_SRC 225241#define CLK_250M_SRC 226242#define CLK_300M_SRC 227243#define CLK_350M_SRC 228244#define CLK_400M_SRC 229245#define CLK_450M_SRC 230246#define CLK_500M_SRC 231247#define CLK_600M_SRC 232248#define CLK_650M_SRC 233249#define CLK_700M_SRC 234250#define CLK_800M_SRC 235251#define CLK_1000M_SRC 236252#define CLK_1200M_SRC 237253#define ACLK_TOP_M300_ROOT 238254#define ACLK_TOP_M500_ROOT 239255#define ACLK_TOP_M400_ROOT 240256#define ACLK_TOP_S200_ROOT 241257#define ACLK_TOP_S400_ROOT 242258#define CLK_MIPI_CAMARAOUT_M0 243259#define CLK_MIPI_CAMARAOUT_M1 244260#define CLK_MIPI_CAMARAOUT_M2 245261#define CLK_MIPI_CAMARAOUT_M3 246262#define CLK_MIPI_CAMARAOUT_M4 247263#define MCLK_GMAC0_OUT 248264#define REFCLKO25M_ETH0_OUT 249265#define REFCLKO25M_ETH1_OUT 250266#define CLK_CIFOUT_OUT 251267#define PCLK_MIPI_DCPHY0 252268#define PCLK_MIPI_DCPHY1 253269#define PCLK_CSIPHY0 254270#define PCLK_CSIPHY1 255271#define ACLK_TOP_ROOT 256272#define PCLK_TOP_ROOT 257273#define ACLK_LOW_TOP_ROOT 258274#define PCLK_CRU 259275#define PCLK_GPU_ROOT 260276#define CLK_GPU_SRC 261277#define CLK_GPU 262278#define CLK_GPU_COREGROUP 263279#define CLK_GPU_STACKS 264280#define PCLK_GPU_PVTM 265281#define CLK_GPU_PVTM 266282#define CLK_CORE_GPU_PVTM 267283#define PCLK_GPU_GRF 268284#define ACLK_ISP1_ROOT 269285#define HCLK_ISP1_ROOT 270286#define CLK_ISP1_CORE 271287#define CLK_ISP1_CORE_MARVIN 272288#define CLK_ISP1_CORE_VICAP 273289#define ACLK_ISP1 274290#define HCLK_ISP1 275291#define ACLK_NPU1 276292#define HCLK_NPU1 277293#define ACLK_NPU2 278294#define HCLK_NPU2 279295#define HCLK_NPU_CM0_ROOT 280296#define FCLK_NPU_CM0_CORE 281297#define CLK_NPU_CM0_RTC 282298#define PCLK_NPU_PVTM 283299#define PCLK_NPU_GRF 284300#define CLK_NPU_PVTM 285301#define CLK_CORE_NPU_PVTM 286302#define ACLK_NPU0 287303#define HCLK_NPU0 288304#define HCLK_NPU_ROOT 289305#define CLK_NPU_DSU0 290306#define PCLK_NPU_ROOT 291307#define PCLK_NPU_TIMER 292308#define CLK_NPUTIMER_ROOT 293309#define CLK_NPUTIMER0 294310#define CLK_NPUTIMER1 295311#define PCLK_NPU_WDT 296312#define TCLK_NPU_WDT 297313#define HCLK_EMMC 298314#define ACLK_EMMC 299315#define CCLK_EMMC 300316#define BCLK_EMMC 301317#define TMCLK_EMMC 302318#define SCLK_SFC 303319#define HCLK_SFC 304320#define HCLK_SFC_XIP 305321#define HCLK_NVM_ROOT 306322#define ACLK_NVM_ROOT 307323#define CLK_GMAC0_PTP_REF 308324#define CLK_GMAC1_PTP_REF 309325#define CLK_GMAC_125M 310326#define CLK_GMAC_50M 311327#define ACLK_PHP_GIC_ITS 312328#define ACLK_MMU_PCIE 313329#define ACLK_MMU_PHP 314330#define ACLK_PCIE_4L_DBI 315331#define ACLK_PCIE_2L_DBI 316332#define ACLK_PCIE_1L0_DBI 317333#define ACLK_PCIE_1L1_DBI 318334#define ACLK_PCIE_1L2_DBI 319335#define ACLK_PCIE_4L_MSTR 320336#define ACLK_PCIE_2L_MSTR 321337#define ACLK_PCIE_1L0_MSTR 322338#define ACLK_PCIE_1L1_MSTR 323339#define ACLK_PCIE_1L2_MSTR 324340#define ACLK_PCIE_4L_SLV 325341#define ACLK_PCIE_2L_SLV 326342#define ACLK_PCIE_1L0_SLV 327343#define ACLK_PCIE_1L1_SLV 328344#define ACLK_PCIE_1L2_SLV 329345#define PCLK_PCIE_4L 330346#define PCLK_PCIE_2L 331347#define PCLK_PCIE_1L0 332348#define PCLK_PCIE_1L1 333349#define PCLK_PCIE_1L2 334350#define CLK_PCIE_AUX0 335351#define CLK_PCIE_AUX1 336352#define CLK_PCIE_AUX2 337353#define CLK_PCIE_AUX3 338354#define CLK_PCIE_AUX4 339355#define CLK_PIPEPHY0_REF 340356#define CLK_PIPEPHY1_REF 341357#define CLK_PIPEPHY2_REF 342358#define PCLK_PHP_ROOT 343359#define PCLK_GMAC0 344360#define PCLK_GMAC1 345361#define ACLK_PCIE_ROOT 346362#define ACLK_PHP_ROOT 347363#define ACLK_PCIE_BRIDGE 348364#define ACLK_GMAC0 349365#define ACLK_GMAC1 350366#define CLK_PMALIVE0 351367#define CLK_PMALIVE1 352368#define CLK_PMALIVE2 353369#define ACLK_SATA0 354370#define ACLK_SATA1 355371#define ACLK_SATA2 356372#define CLK_RXOOB0 357373#define CLK_RXOOB1 358374#define CLK_RXOOB2 359375#define ACLK_USB3OTG2 360376#define SUSPEND_CLK_USB3OTG2 361377#define REF_CLK_USB3OTG2 362378#define CLK_UTMI_OTG2 363379#define CLK_PIPEPHY0_PIPE_G 364380#define CLK_PIPEPHY1_PIPE_G 365381#define CLK_PIPEPHY2_PIPE_G 366382#define CLK_PIPEPHY0_PIPE_ASIC_G 367383#define CLK_PIPEPHY1_PIPE_ASIC_G 368384#define CLK_PIPEPHY2_PIPE_ASIC_G 369385#define CLK_PIPEPHY2_PIPE_U3_G 370386#define CLK_PCIE1L2_PIPE 371387#define CLK_PCIE4L_PIPE 372388#define CLK_PCIE2L_PIPE 373389#define PCLK_PCIE_COMBO_PIPE_PHY0 374390#define PCLK_PCIE_COMBO_PIPE_PHY1 375391#define PCLK_PCIE_COMBO_PIPE_PHY2 376392#define PCLK_PCIE_COMBO_PIPE_PHY 377393#define HCLK_RGA3_1 378394#define ACLK_RGA3_1 379395#define CLK_RGA3_1_CORE 380396#define ACLK_RGA3_ROOT 381397#define HCLK_RGA3_ROOT 382398#define ACLK_RKVDEC_CCU 383399#define HCLK_RKVDEC0 384400#define ACLK_RKVDEC0 385401#define CLK_RKVDEC0_CA 386402#define CLK_RKVDEC0_HEVC_CA 387403#define CLK_RKVDEC0_CORE 388404#define HCLK_RKVDEC1 389405#define ACLK_RKVDEC1 390406#define CLK_RKVDEC1_CA 391407#define CLK_RKVDEC1_HEVC_CA 392408#define CLK_RKVDEC1_CORE 393409#define HCLK_SDIO 394410#define CCLK_SRC_SDIO 395411#define ACLK_USB_ROOT 396412#define HCLK_USB_ROOT 397413#define HCLK_HOST0 398414#define HCLK_HOST_ARB0 399415#define HCLK_HOST1 400416#define HCLK_HOST_ARB1 401417#define ACLK_USB3OTG0 402418#define SUSPEND_CLK_USB3OTG0 403419#define REF_CLK_USB3OTG0 404420#define ACLK_USB3OTG1 405421#define SUSPEND_CLK_USB3OTG1 406422#define REF_CLK_USB3OTG1 407423#define UTMI_OHCI_CLK48_HOST0 408424#define UTMI_OHCI_CLK48_HOST1 409425#define HCLK_IEP2P0 410426#define ACLK_IEP2P0 411427#define CLK_IEP2P0_CORE 412428#define ACLK_JPEG_ENCODER0 413429#define HCLK_JPEG_ENCODER0 414430#define ACLK_JPEG_ENCODER1 415431#define HCLK_JPEG_ENCODER1 416432#define ACLK_JPEG_ENCODER2 417433#define HCLK_JPEG_ENCODER2 418434#define ACLK_JPEG_ENCODER3 419435#define HCLK_JPEG_ENCODER3 420436#define ACLK_JPEG_DECODER 421437#define HCLK_JPEG_DECODER 422438#define HCLK_RGA2 423439#define ACLK_RGA2 424440#define CLK_RGA2_CORE 425441#define HCLK_RGA3_0 426442#define ACLK_RGA3_0 427443#define CLK_RGA3_0_CORE 428444#define ACLK_VDPU_ROOT 429445#define ACLK_VDPU_LOW_ROOT 430446#define HCLK_VDPU_ROOT 431447#define ACLK_JPEG_DECODER_ROOT 432448#define ACLK_VPU 433449#define HCLK_VPU 434450#define HCLK_RKVENC0_ROOT 435451#define ACLK_RKVENC0_ROOT 436452#define HCLK_RKVENC0 437453#define ACLK_RKVENC0 438454#define CLK_RKVENC0_CORE 439455#define HCLK_RKVENC1_ROOT 440456#define ACLK_RKVENC1_ROOT 441457#define HCLK_RKVENC1 442458#define ACLK_RKVENC1 443459#define CLK_RKVENC1_CORE 444460#define ICLK_CSIHOST01 445461#define ICLK_CSIHOST0 446462#define ICLK_CSIHOST1 447463#define PCLK_CSI_HOST_0 448464#define PCLK_CSI_HOST_1 449465#define PCLK_CSI_HOST_2 450466#define PCLK_CSI_HOST_3 451467#define PCLK_CSI_HOST_4 452468#define PCLK_CSI_HOST_5 453469#define ACLK_FISHEYE0 454470#define HCLK_FISHEYE0 455471#define CLK_FISHEYE0_CORE 456472#define ACLK_FISHEYE1 457473#define HCLK_FISHEYE1 458474#define CLK_FISHEYE1_CORE 459475#define CLK_ISP0_CORE 460476#define CLK_ISP0_CORE_MARVIN 461477#define CLK_ISP0_CORE_VICAP 462478#define ACLK_ISP0 463479#define HCLK_ISP0 464480#define ACLK_VI_ROOT 465481#define HCLK_VI_ROOT 466482#define PCLK_VI_ROOT 467483#define DCLK_VICAP 468484#define ACLK_VICAP 469485#define HCLK_VICAP 470486#define PCLK_DP0 471487#define PCLK_DP1 472488#define PCLK_S_DP0 473489#define PCLK_S_DP1 474490#define CLK_DP0 475491#define CLK_DP1 476492#define HCLK_HDCP_KEY0 477493#define ACLK_HDCP0 478494#define HCLK_HDCP0 479495#define PCLK_HDCP0 480496#define HCLK_I2S4_8CH 481497#define ACLK_TRNG0 482498#define PCLK_TRNG0 483499#define ACLK_VO0_ROOT 484500#define HCLK_VO0_ROOT 485501#define HCLK_VO0_S_ROOT 486502#define PCLK_VO0_ROOT 487503#define PCLK_VO0_S_ROOT 488504#define PCLK_VO0GRF 489505#define CLK_I2S4_8CH_TX_SRC 490506#define CLK_I2S4_8CH_TX_FRAC 491507#define MCLK_I2S4_8CH_TX 492508#define CLK_I2S4_8CH_TX 493509#define HCLK_I2S8_8CH 494510#define CLK_I2S8_8CH_TX_SRC 495511#define CLK_I2S8_8CH_TX_FRAC 496512#define MCLK_I2S8_8CH_TX 497513#define CLK_I2S8_8CH_TX 498514#define HCLK_SPDIF2_DP0 499515#define CLK_SPDIF2_DP0_SRC 500516#define CLK_SPDIF2_DP0_FRAC 501517#define MCLK_SPDIF2_DP0 502518#define CLK_SPDIF2_DP0 503519#define MCLK_SPDIF2 504520#define HCLK_SPDIF5_DP1 505521#define CLK_SPDIF5_DP1_SRC 506522#define CLK_SPDIF5_DP1_FRAC 507523#define MCLK_SPDIF5_DP1 508524#define CLK_SPDIF5_DP1 509525#define MCLK_SPDIF5 510526#define PCLK_EDP0 511527#define CLK_EDP0_24M 512528#define CLK_EDP0_200M 513529#define PCLK_EDP1 514530#define CLK_EDP1_24M 515531#define CLK_EDP1_200M 516532#define HCLK_HDCP_KEY1 517533#define ACLK_HDCP1 518534#define HCLK_HDCP1 519535#define PCLK_HDCP1 520536#define ACLK_HDMIRX 521537#define PCLK_HDMIRX 522538#define CLK_HDMIRX_REF 523539#define CLK_HDMIRX_AUD_SRC 524540#define CLK_HDMIRX_AUD_FRAC 525541#define CLK_HDMIRX_AUD 526542#define CLK_HDMIRX_AUD_P_MUX 527543#define PCLK_HDMITX0 528544#define CLK_HDMITX0_EARC 529545#define CLK_HDMITX0_REF 530546#define PCLK_HDMITX1 531547#define CLK_HDMITX1_EARC 532548#define CLK_HDMITX1_REF 533549#define CLK_HDMITRX_REFSRC 534550#define ACLK_TRNG1 535551#define PCLK_TRNG1 536552#define ACLK_HDCP1_ROOT 537553#define ACLK_HDMIRX_ROOT 538554#define HCLK_VO1_ROOT 539555#define HCLK_VO1_S_ROOT 540556#define PCLK_VO1_ROOT 541557#define PCLK_VO1_S_ROOT 542558#define PCLK_S_EDP0 543559#define PCLK_S_EDP1 544560#define PCLK_S_HDMIRX 545561#define HCLK_I2S10_8CH 546562#define CLK_I2S10_8CH_RX_SRC 547563#define CLK_I2S10_8CH_RX_FRAC 548564#define CLK_I2S10_8CH_RX 549565#define MCLK_I2S10_8CH_RX 550566#define HCLK_I2S7_8CH 551567#define CLK_I2S7_8CH_RX_SRC 552568#define CLK_I2S7_8CH_RX_FRAC 553569#define CLK_I2S7_8CH_RX 554570#define MCLK_I2S7_8CH_RX 555571#define HCLK_I2S9_8CH 556572#define CLK_I2S9_8CH_RX_SRC 557573#define CLK_I2S9_8CH_RX_FRAC 558574#define CLK_I2S9_8CH_RX 559575#define MCLK_I2S9_8CH_RX 560576#define CLK_I2S5_8CH_TX_SRC 561577#define CLK_I2S5_8CH_TX_FRAC 562578#define CLK_I2S5_8CH_TX 563579#define MCLK_I2S5_8CH_TX 564580#define HCLK_I2S5_8CH 565581#define CLK_I2S6_8CH_TX_SRC 566582#define CLK_I2S6_8CH_TX_FRAC 567583#define CLK_I2S6_8CH_TX 568584#define MCLK_I2S6_8CH_TX 569585#define CLK_I2S6_8CH_RX_SRC 570586#define CLK_I2S6_8CH_RX_FRAC 571587#define CLK_I2S6_8CH_RX 572588#define MCLK_I2S6_8CH_RX 573589#define I2S6_8CH_MCLKOUT 574590#define HCLK_I2S6_8CH 575591#define HCLK_SPDIF3 576592#define CLK_SPDIF3_SRC 577593#define CLK_SPDIF3_FRAC 578594#define CLK_SPDIF3 579595#define MCLK_SPDIF3 580596#define HCLK_SPDIF4 581597#define CLK_SPDIF4_SRC 582598#define CLK_SPDIF4_FRAC 583599#define CLK_SPDIF4 584600#define MCLK_SPDIF4 585601#define HCLK_SPDIFRX0 586602#define MCLK_SPDIFRX0 587603#define HCLK_SPDIFRX1 588604#define MCLK_SPDIFRX1 589605#define HCLK_SPDIFRX2 590606#define MCLK_SPDIFRX2 591607#define ACLK_VO1USB_TOP_ROOT 592608#define HCLK_VO1USB_TOP_ROOT 593609#define CLK_HDMIHDP0 594610#define CLK_HDMIHDP1 595611#define PCLK_HDPTX0 596612#define PCLK_HDPTX1 597613#define PCLK_USBDPPHY0 598614#define PCLK_USBDPPHY1 599615#define ACLK_VOP_ROOT 600616#define ACLK_VOP_LOW_ROOT 601617#define HCLK_VOP_ROOT 602618#define PCLK_VOP_ROOT 603619#define HCLK_VOP 604620#define ACLK_VOP 605621#define DCLK_VOP0_SRC 606622#define DCLK_VOP1_SRC 607623#define DCLK_VOP2_SRC 608624#define DCLK_VOP0 609625#define DCLK_VOP1 610626#define DCLK_VOP2 611627#define DCLK_VOP3 612628#define PCLK_DSIHOST0 613629#define PCLK_DSIHOST1 614630#define CLK_DSIHOST0 615631#define CLK_DSIHOST1 616632#define CLK_VOP_PMU 617633#define ACLK_VOP_DOBY 618634#define ACLK_VOP_SUB_SRC 619635#define CLK_USBDP_PHY0_IMMORTAL 620636#define CLK_USBDP_PHY1_IMMORTAL 621637#define CLK_PMU0 622638#define PCLK_PMU0 623639#define PCLK_PMU0IOC 624640#define PCLK_GPIO0 625641#define DBCLK_GPIO0 626642#define PCLK_I2C0 627643#define CLK_I2C0 628644#define HCLK_I2S1_8CH 629645#define CLK_I2S1_8CH_TX_SRC 630646#define CLK_I2S1_8CH_TX_FRAC 631647#define CLK_I2S1_8CH_TX 632648#define MCLK_I2S1_8CH_TX 633649#define CLK_I2S1_8CH_RX_SRC 634650#define CLK_I2S1_8CH_RX_FRAC 635651#define CLK_I2S1_8CH_RX 636652#define MCLK_I2S1_8CH_RX 637653#define I2S1_8CH_MCLKOUT 638654#define CLK_PMU1_50M_SRC 639655#define CLK_PMU1_100M_SRC 640656#define CLK_PMU1_200M_SRC 641657#define CLK_PMU1_300M_SRC 642658#define CLK_PMU1_400M_SRC 643659#define HCLK_PMU1_ROOT 644660#define PCLK_PMU1_ROOT 645661#define PCLK_PMU0_ROOT 646662#define HCLK_PMU_CM0_ROOT 647663#define PCLK_PMU1 648664#define CLK_DDR_FAIL_SAFE 649665#define CLK_PMU1 650666#define HCLK_PDM0 651667#define MCLK_PDM0 652668#define HCLK_VAD 653669#define FCLK_PMU_CM0_CORE 654670#define CLK_PMU_CM0_RTC 655671#define PCLK_PMU1_IOC 656672#define PCLK_PMU1PWM 657673#define CLK_PMU1PWM 658674#define CLK_PMU1PWM_CAPTURE 659675#define PCLK_PMU1TIMER 660676#define CLK_PMU1TIMER_ROOT 661677#define CLK_PMU1TIMER0 662678#define CLK_PMU1TIMER1 663679#define CLK_UART0_SRC 664680#define CLK_UART0_FRAC 665681#define CLK_UART0 666682#define SCLK_UART0 667683#define PCLK_UART0 668684#define PCLK_PMU1WDT 669685#define TCLK_PMU1WDT 670686#define CLK_CR_PARA 671687#define CLK_USB2PHY_HDPTXRXPHY_REF 672688#define CLK_USBDPPHY_MIPIDCPPHY_REF 673689#define CLK_REF_PIPE_PHY0_OSC_SRC 674690#define CLK_REF_PIPE_PHY1_OSC_SRC 675691#define CLK_REF_PIPE_PHY2_OSC_SRC 676692#define CLK_REF_PIPE_PHY0_PLL_SRC 677693#define CLK_REF_PIPE_PHY1_PLL_SRC 678694#define CLK_REF_PIPE_PHY2_PLL_SRC 679695#define CLK_REF_PIPE_PHY0 680696#define CLK_REF_PIPE_PHY1 681697#define CLK_REF_PIPE_PHY2 682698#define SCLK_SDIO_DRV 683699#define SCLK_SDIO_SAMPLE 684700#define SCLK_SDMMC_DRV 685701#define SCLK_SDMMC_SAMPLE 686702#define CLK_PCIE1L0_PIPE 687703#define CLK_PCIE1L1_PIPE 688704#define CLK_BIGCORE0_PVTM 689705#define CLK_CORE_BIGCORE0_PVTM 690706#define CLK_BIGCORE1_PVTM 691707#define CLK_CORE_BIGCORE1_PVTM 692708#define CLK_LITCORE_PVTM 693709#define CLK_CORE_LITCORE_PVTM 694710#define CLK_AUX16M_0 695711#define CLK_AUX16M_1 696712#define CLK_PHY0_REF_ALT_P 697713#define CLK_PHY0_REF_ALT_M 698714#define CLK_PHY1_REF_ALT_P 699715#define CLK_PHY1_REF_ALT_M 700716#define ACLK_ISP1_PRE 701717#define HCLK_ISP1_PRE 702718#define HCLK_NVM 703719#define ACLK_USB 704720#define HCLK_USB 705721#define ACLK_JPEG_DECODER_PRE 706722#define ACLK_VDPU_LOW_PRE 707723#define ACLK_RKVENC1_PRE 708724#define HCLK_RKVENC1_PRE 709725#define HCLK_RKVDEC0_PRE 710726#define ACLK_RKVDEC0_PRE 711727#define HCLK_RKVDEC1_PRE 712728#define ACLK_RKVDEC1_PRE 713729#define ACLK_HDCP0_PRE 714730#define HCLK_VO0 715731#define ACLK_HDCP1_PRE 716732#define HCLK_VO1 717733#define ACLK_AV1_PRE 718734#define PCLK_AV1_PRE 719735#define HCLK_SDIO_PRE 720736#define PCLK_VO1GRF 721737 738/* scmi-clocks indices */739 740#define SCMI_CLK_CPUL 0741#define SCMI_CLK_DSU 1742#define SCMI_CLK_CPUB01 2743#define SCMI_CLK_CPUB23 3744#define SCMI_CLK_DDR 4745#define SCMI_CLK_GPU 5746#define SCMI_CLK_NPU 6747#define SCMI_CLK_SBUS 7748#define SCMI_PCLK_SBUS 8749#define SCMI_CCLK_SD 9750#define SCMI_DCLK_SD 10751#define SCMI_ACLK_SECURE_NS 11752#define SCMI_HCLK_SECURE_NS 12753#define SCMI_TCLK_WDT 13754#define SCMI_KEYLADDER_CORE 14755#define SCMI_KEYLADDER_RNG 15756#define SCMI_ACLK_SECURE_S 16757#define SCMI_HCLK_SECURE_S 17758#define SCMI_PCLK_SECURE_S 18759#define SCMI_CRYPTO_RNG 19760#define SCMI_CRYPTO_CORE 20761#define SCMI_CRYPTO_PKA 21762#define SCMI_SPLL 22763#define SCMI_HCLK_SD 23764 765#endif766