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1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */2/*3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd.4 * Author: Finley Xiao <finley.xiao@rock-chips.com>5 */6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H8#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H9 10/* pmucru-clocks indices */11 12/* pll clocks */13#define PLL_GPLL 114 15/* sclk (special clocks) */16#define CLK_OSC0_DIV32K 217#define CLK_RTC32K 318#define CLK_WIFI_DIV 419#define CLK_WIFI_OSC0 520#define CLK_WIFI 621#define CLK_PMU 722#define SCLK_UART1_DIV 823#define SCLK_UART1_FRACDIV 924#define SCLK_UART1_MUX 1025#define SCLK_UART1 1126#define CLK_I2C0 1227#define CLK_I2C2 1328#define CLK_CAPTURE_PWM0 1429#define CLK_PWM0 1530#define CLK_CAPTURE_PWM1 1631#define CLK_PWM1 1732#define CLK_SPI0 1833#define DBCLK_GPIO0 1934#define CLK_PMUPVTM 2035#define CLK_CORE_PMUPVTM 2136#define CLK_REF12M 2237#define CLK_USBPHY_OTG_REF 2338#define CLK_USBPHY_HOST_REF 2439#define CLK_REF24M 2540#define CLK_MIPIDSIPHY_REF 2641 42/* pclk */43#define PCLK_PDPMU 3044#define PCLK_PMU 3145#define PCLK_UART1 3246#define PCLK_I2C0 3347#define PCLK_I2C2 3448#define PCLK_PWM0 3549#define PCLK_PWM1 3650#define PCLK_SPI0 3751#define PCLK_GPIO0 3852#define PCLK_PMUSGRF 3953#define PCLK_PMUGRF 4054#define PCLK_PMUCRU 4155#define PCLK_CHIPVEROTP 4256#define PCLK_PDPMU_NIU 4357#define PCLK_PMUPVTM 4458#define PCLK_SCRKEYGEN 4559 60#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)61 62/* cru-clocks indices */63 64/* pll clocks */65#define PLL_APLL 166#define PLL_DPLL 267#define PLL_CPLL 368#define PLL_HPLL 469 70/* sclk (special clocks) */71#define ARMCLK 572#define USB480M 673#define CLK_CORE_CPUPVTM 774#define CLK_CPUPVTM 875#define CLK_SCR1 976#define CLK_SCR1_CORE 1077#define CLK_SCR1_RTC 1178#define CLK_SCR1_JTAG 1279#define SCLK_UART0_DIV 1380#define SCLK_UART0_FRAC 1481#define SCLK_UART0_MUX 1582#define SCLK_UART0 1683#define SCLK_UART2_DIV 1784#define SCLK_UART2_FRAC 1885#define SCLK_UART2_MUX 1986#define SCLK_UART2 2087#define SCLK_UART3_DIV 2188#define SCLK_UART3_FRAC 2289#define SCLK_UART3_MUX 2390#define SCLK_UART3 2491#define SCLK_UART4_DIV 2592#define SCLK_UART4_FRAC 2693#define SCLK_UART4_MUX 2794#define SCLK_UART4 2895#define SCLK_UART5_DIV 2996#define SCLK_UART5_FRAC 3097#define SCLK_UART5_MUX 3198#define SCLK_UART5 3299#define CLK_I2C1 33100#define CLK_I2C3 34101#define CLK_I2C4 35102#define CLK_I2C5 36103#define CLK_SPI1 37104#define CLK_CAPTURE_PWM2 38105#define CLK_PWM2 39106#define DBCLK_GPIO1 40107#define DBCLK_GPIO2 41108#define DBCLK_GPIO3 42109#define DBCLK_GPIO4 43110#define CLK_SARADC 44111#define CLK_TIMER0 45112#define CLK_TIMER1 46113#define CLK_TIMER2 47114#define CLK_TIMER3 48115#define CLK_TIMER4 49116#define CLK_TIMER5 50117#define CLK_CAN 51118#define CLK_NPU_TSADC 52119#define CLK_NPU_TSADCPHY 53120#define CLK_CPU_TSADC 54121#define CLK_CPU_TSADCPHY 55122#define CLK_CRYPTO_CORE 56123#define CLK_CRYPTO_PKA 57124#define MCLK_I2S0_TX_DIV 58125#define MCLK_I2S0_TX_FRACDIV 59126#define MCLK_I2S0_TX_MUX 60127#define MCLK_I2S0_TX 61128#define MCLK_I2S0_RX_DIV 62129#define MCLK_I2S0_RX_FRACDIV 63130#define MCLK_I2S0_RX_MUX 64131#define MCLK_I2S0_RX 65132#define MCLK_I2S0_TX_OUT2IO 66133#define MCLK_I2S0_RX_OUT2IO 67134#define MCLK_I2S1_DIV 68135#define MCLK_I2S1_FRACDIV 69136#define MCLK_I2S1_MUX 70137#define MCLK_I2S1 71138#define MCLK_I2S1_OUT2IO 72139#define MCLK_I2S2_DIV 73140#define MCLK_I2S2_FRACDIV 74141#define MCLK_I2S2_MUX 75142#define MCLK_I2S2 76143#define MCLK_I2S2_OUT2IO 77144#define MCLK_PDM 78145#define SCLK_ADUPWM_DIV 79146#define SCLK_AUDPWM_FRACDIV 80147#define SCLK_AUDPWM_MUX 81148#define SCLK_AUDPWM 82149#define CLK_ACDCDIG_ADC 83150#define CLK_ACDCDIG_DAC 84151#define CLK_ACDCDIG_I2C 85152#define CLK_VENC_CORE 86153#define CLK_VDEC_CORE 87154#define CLK_VDEC_CA 88155#define CLK_VDEC_HEVC_CA 89156#define CLK_RGA_CORE 90157#define CLK_IEP_CORE 91158#define CLK_ISP_DIV 92159#define CLK_ISP_NP5 93160#define CLK_ISP_NUX 94161#define CLK_ISP 95162#define CLK_CIF_OUT_DIV 96163#define CLK_CIF_OUT_FRACDIV 97164#define CLK_CIF_OUT_MUX 98165#define CLK_CIF_OUT 99166#define CLK_MIPICSI_OUT_DIV 100167#define CLK_MIPICSI_OUT_FRACDIV 101168#define CLK_MIPICSI_OUT_MUX 102169#define CLK_MIPICSI_OUT 103170#define CLK_ISPP_DIV 104171#define CLK_ISPP_NP5 105172#define CLK_ISPP_NUX 106173#define CLK_ISPP 107174#define CLK_SDMMC 108175#define SCLK_SDMMC_DRV 109176#define SCLK_SDMMC_SAMPLE 110177#define CLK_SDIO 111178#define SCLK_SDIO_DRV 112179#define SCLK_SDIO_SAMPLE 113180#define CLK_EMMC 114181#define SCLK_EMMC_DRV 115182#define SCLK_EMMC_SAMPLE 116183#define CLK_NANDC 117184#define SCLK_SFC 118185#define CLK_USBHOST_UTMI_OHCI 119186#define CLK_USBOTG_REF 120187#define CLK_GMAC_DIV 121188#define CLK_GMAC_RGMII_M0 122189#define CLK_GMAC_SRC_M0 123190#define CLK_GMAC_RGMII_M1 124191#define CLK_GMAC_SRC_M1 125192#define CLK_GMAC_SRC 126193#define CLK_GMAC_REF 127194#define CLK_GMAC_TX_SRC 128195#define CLK_GMAC_TX_DIV5 129196#define CLK_GMAC_TX_DIV50 130197#define RGMII_MODE_CLK 131198#define CLK_GMAC_RX_SRC 132199#define CLK_GMAC_RX_DIV2 133200#define CLK_GMAC_RX_DIV20 134201#define RMII_MODE_CLK 135202#define CLK_GMAC_TX_RX 136203#define CLK_GMAC_PTPREF 137204#define CLK_GMAC_ETHERNET_OUT 138205#define CLK_DDRPHY 139206#define CLK_DDR_MON 140207#define TMCLK_DDR_MON 141208#define CLK_NPU_DIV 142209#define CLK_NPU_NP5 143210#define CLK_CORE_NPU 144211#define CLK_CORE_NPUPVTM 145212#define CLK_NPUPVTM 146213#define SCLK_DDRCLK 147214#define CLK_OTP 148215 216/* dclk */217#define DCLK_DECOM 150218#define DCLK_VOP_DIV 151219#define DCLK_VOP_FRACDIV 152220#define DCLK_VOP_MUX 153221#define DCLK_VOP 154222#define DCLK_CIF 155223#define DCLK_CIFLITE 156224 225/* aclk */226#define ACLK_PDBUS 160227#define ACLK_DMAC 161228#define ACLK_DCF 162229#define ACLK_SPINLOCK 163230#define ACLK_DECOM 164231#define ACLK_PDCRYPTO 165232#define ACLK_CRYPTO 166233#define ACLK_PDVEPU 167234#define ACLK_VENC 168235#define ACLK_PDVDEC 169236#define ACLK_PDJPEG 170237#define ACLK_VDEC 171238#define ACLK_JPEG 172239#define ACLK_PDVO 173240#define ACLK_RGA 174241#define ACLK_VOP 175242#define ACLK_IEP 176243#define ACLK_PDVI_DIV 177244#define ACLK_PDVI_NP5 178245#define ACLK_PDVI 179246#define ACLK_ISP 180247#define ACLK_CIF 181248#define ACLK_CIFLITE 182249#define ACLK_PDISPP_DIV 183250#define ACLK_PDISPP_NP5 184251#define ACLK_PDISPP 185252#define ACLK_ISPP 186253#define ACLK_PDPHP 187254#define ACLK_PDUSB 188255#define ACLK_USBOTG 189256#define ACLK_PDGMAC 190257#define ACLK_GMAC 191258#define ACLK_PDNPU_DIV 192259#define ACLK_PDNPU_NP5 193260#define ACLK_PDNPU 194261#define ACLK_NPU 195262 263/* hclk */264#define HCLK_PDCORE_NIU 200265#define HCLK_PDUSB 201266#define HCLK_PDCRYPTO 202267#define HCLK_CRYPTO 203268#define HCLK_PDAUDIO 204269#define HCLK_I2S0 205270#define HCLK_I2S1 206271#define HCLK_I2S2 207272#define HCLK_PDM 208273#define HCLK_AUDPWM 209274#define HCLK_PDVEPU 210275#define HCLK_VENC 211276#define HCLK_PDVDEC 212277#define HCLK_PDJPEG 213278#define HCLK_VDEC 214279#define HCLK_JPEG 215280#define HCLK_PDVO 216281#define HCLK_RGA 217282#define HCLK_VOP 218283#define HCLK_IEP 219284#define HCLK_PDVI 220285#define HCLK_ISP 221286#define HCLK_CIF 222287#define HCLK_CIFLITE 223288#define HCLK_PDISPP 224289#define HCLK_ISPP 225290#define HCLK_PDPHP 226291#define HCLK_PDSDMMC 227292#define HCLK_SDMMC 228293#define HCLK_PDSDIO 229294#define HCLK_SDIO 230295#define HCLK_PDNVM 231296#define HCLK_EMMC 232297#define HCLK_NANDC 233298#define HCLK_SFC 234299#define HCLK_SFCXIP 235300#define HCLK_PDBUS 236301#define HCLK_USBHOST 237302#define HCLK_USBHOST_ARB 238303#define HCLK_PDNPU 239304#define HCLK_NPU 240305 306/* pclk */307#define PCLK_CPUPVTM 245308#define PCLK_PDBUS 246309#define PCLK_DCF 247310#define PCLK_WDT 248311#define PCLK_MAILBOX 249312#define PCLK_UART0 250313#define PCLK_UART2 251314#define PCLK_UART3 252315#define PCLK_UART4 253316#define PCLK_UART5 254317#define PCLK_I2C1 255318#define PCLK_I2C3 256319#define PCLK_I2C4 257320#define PCLK_I2C5 258321#define PCLK_SPI1 259322#define PCLK_PWM2 261323#define PCLK_GPIO1 262324#define PCLK_GPIO2 263325#define PCLK_GPIO3 264326#define PCLK_GPIO4 265327#define PCLK_SARADC 266328#define PCLK_TIMER 267329#define PCLK_DECOM 268330#define PCLK_CAN 269331#define PCLK_NPU_TSADC 270332#define PCLK_CPU_TSADC 271333#define PCLK_ACDCDIG 272334#define PCLK_PDVO 273335#define PCLK_DSIHOST 274336#define PCLK_PDVI 275337#define PCLK_CSIHOST 276338#define PCLK_PDGMAC 277339#define PCLK_GMAC 278340#define PCLK_PDDDR 279341#define PCLK_DDR_MON 280342#define PCLK_PDNPU 281343#define PCLK_NPUPVTM 282344#define PCLK_PDTOP 283345#define PCLK_TOPCRU 284346#define PCLK_TOPGRF 285347#define PCLK_CPUEMADET 286348#define PCLK_DDRPHY 287349#define PCLK_DSIPHY 289350#define PCLK_CSIPHY0 290351#define PCLK_CSIPHY1 291352#define PCLK_USBPHY_HOST 292353#define PCLK_USBPHY_OTG 293354#define PCLK_OTP 294355 356#define CLK_NR_CLKS (PCLK_OTP + 1)357 358/* pmu soft-reset indices */359 360/* pmu_cru_softrst_con0 */361#define SRST_PDPMU_NIU_P 0362#define SRST_PMU_SGRF_P 1363#define SRST_PMU_SGRF_REMAP_P 2364#define SRST_I2C0_P 3365#define SRST_I2C0 4366#define SRST_I2C2_P 7367#define SRST_I2C2 8368#define SRST_UART1_P 9369#define SRST_UART1 10370#define SRST_PWM0_P 11371#define SRST_PWM0 12372#define SRST_PWM1_P 13373#define SRST_PWM1 14374#define SRST_DDR_FAIL_SAFE 15375 376/* pmu_cru_softrst_con1 */377#define SRST_GPIO0_P 17378#define SRST_GPIO0_DB 18379#define SRST_SPI0_P 19380#define SRST_SPI0 20381#define SRST_PMUGRF_P 21382#define SRST_CHIPVEROTP_P 22383#define SRST_PMUPVTM 24384#define SRST_PMUPVTM_P 25385#define SRST_PMUCRU_P 30386 387/* soft-reset indices */388 389/* cru_softrst_con0 */390#define SRST_CORE0_PO 0391#define SRST_CORE1_PO 1392#define SRST_CORE2_PO 2393#define SRST_CORE3_PO 3394#define SRST_CORE0 4395#define SRST_CORE1 5396#define SRST_CORE2 6397#define SRST_CORE3 7398#define SRST_CORE0_DBG 8399#define SRST_CORE1_DBG 9400#define SRST_CORE2_DBG 10401#define SRST_CORE3_DBG 11402#define SRST_NL2 12403#define SRST_CORE_NIU_A 13404#define SRST_DBG_DAPLITE_P 14405#define SRST_DAPLITE_P 15406 407/* cru_softrst_con1 */408#define SRST_PDBUS_NIU1_A 16409#define SRST_PDBUS_NIU1_H 17410#define SRST_PDBUS_NIU1_P 18411#define SRST_PDBUS_NIU2_A 19412#define SRST_PDBUS_NIU2_H 20413#define SRST_PDBUS_NIU3_A 21414#define SRST_PDBUS_NIU3_H 22415#define SRST_PDBUS_HOLD_NIU1_A 23416#define SRST_DBG_NIU_P 24417#define SRST_PDCORE_NIIU_H 25418#define SRST_MUC_NIU 26419#define SRST_DCF_A 29420#define SRST_DCF_P 30421#define SRST_SYSTEM_SRAM_A 31422 423/* cru_softrst_con2 */424#define SRST_I2C1_P 32425#define SRST_I2C1 33426#define SRST_I2C3_P 34427#define SRST_I2C3 35428#define SRST_I2C4_P 36429#define SRST_I2C4 37430#define SRST_I2C5_P 38431#define SRST_I2C5 39432#define SRST_SPI1_P 40433#define SRST_SPI1 41434#define SRST_MCU_CORE 42435#define SRST_PWM2_P 44436#define SRST_PWM2 45437#define SRST_SPINLOCK_A 46438 439/* cru_softrst_con3 */440#define SRST_UART0_P 48441#define SRST_UART0 49442#define SRST_UART2_P 50443#define SRST_UART2 51444#define SRST_UART3_P 52445#define SRST_UART3 53446#define SRST_UART4_P 54447#define SRST_UART4 55448#define SRST_UART5_P 56449#define SRST_UART5 57450#define SRST_WDT_P 58451#define SRST_SARADC_P 59452#define SRST_GRF_P 61453#define SRST_TIMER_P 62454#define SRST_MAILBOX_P 63455 456/* cru_softrst_con4 */457#define SRST_TIMER0 64458#define SRST_TIMER1 65459#define SRST_TIMER2 66460#define SRST_TIMER3 67461#define SRST_TIMER4 68462#define SRST_TIMER5 69463#define SRST_INTMUX_P 70464#define SRST_GPIO1_P 72465#define SRST_GPIO1_DB 73466#define SRST_GPIO2_P 74467#define SRST_GPIO2_DB 75468#define SRST_GPIO3_P 76469#define SRST_GPIO3_DB 77470#define SRST_GPIO4_P 78471#define SRST_GPIO4_DB 79472 473/* cru_softrst_con5 */474#define SRST_CAN_P 80475#define SRST_CAN 81476#define SRST_DECOM_A 85477#define SRST_DECOM_P 86478#define SRST_DECOM_D 87479#define SRST_PDCRYPTO_NIU_A 88480#define SRST_PDCRYPTO_NIU_H 89481#define SRST_CRYPTO_A 90482#define SRST_CRYPTO_H 91483#define SRST_CRYPTO_CORE 92484#define SRST_CRYPTO_PKA 93485#define SRST_SGRF_P 95486 487/* cru_softrst_con6 */488#define SRST_PDAUDIO_NIU_H 96489#define SRST_PDAUDIO_NIU_P 97490#define SRST_I2S0_H 98491#define SRST_I2S0_TX_M 99492#define SRST_I2S0_RX_M 100493#define SRST_I2S1_H 101494#define SRST_I2S1_M 102495#define SRST_I2S2_H 103496#define SRST_I2S2_M 104497#define SRST_PDM_H 105498#define SRST_PDM_M 106499#define SRST_AUDPWM_H 107500#define SRST_AUDPWM 108501#define SRST_ACDCDIG_P 109502#define SRST_ACDCDIG 110503 504/* cru_softrst_con7 */505#define SRST_PDVEPU_NIU_A 112506#define SRST_PDVEPU_NIU_H 113507#define SRST_VENC_A 114508#define SRST_VENC_H 115509#define SRST_VENC_CORE 116510#define SRST_PDVDEC_NIU_A 117511#define SRST_PDVDEC_NIU_H 118512#define SRST_VDEC_A 119513#define SRST_VDEC_H 120514#define SRST_VDEC_CORE 121515#define SRST_VDEC_CA 122516#define SRST_VDEC_HEVC_CA 123517#define SRST_PDJPEG_NIU_A 124518#define SRST_PDJPEG_NIU_H 125519#define SRST_JPEG_A 126520#define SRST_JPEG_H 127521 522/* cru_softrst_con8 */523#define SRST_PDVO_NIU_A 128524#define SRST_PDVO_NIU_H 129525#define SRST_PDVO_NIU_P 130526#define SRST_RGA_A 131527#define SRST_RGA_H 132528#define SRST_RGA_CORE 133529#define SRST_VOP_A 134530#define SRST_VOP_H 135531#define SRST_VOP_D 136532#define SRST_TXBYTEHS_DSIHOST 137533#define SRST_DSIHOST_P 138534#define SRST_IEP_A 139535#define SRST_IEP_H 140536#define SRST_IEP_CORE 141537#define SRST_ISP_RX_P 142538 539/* cru_softrst_con9 */540#define SRST_PDVI_NIU_A 144541#define SRST_PDVI_NIU_H 145542#define SRST_PDVI_NIU_P 146543#define SRST_ISP 147544#define SRST_CIF_A 148545#define SRST_CIF_H 149546#define SRST_CIF_D 150547#define SRST_CIF_P 151548#define SRST_CIF_I 152549#define SRST_CIF_RX_P 153550#define SRST_PDISPP_NIU_A 154551#define SRST_PDISPP_NIU_H 155552#define SRST_ISPP_A 156553#define SRST_ISPP_H 157554#define SRST_ISPP 158555#define SRST_CSIHOST_P 159556 557/* cru_softrst_con10 */558#define SRST_PDPHPMID_NIU_A 160559#define SRST_PDPHPMID_NIU_H 161560#define SRST_PDNVM_NIU_H 163561#define SRST_SDMMC_H 164562#define SRST_SDIO_H 165563#define SRST_EMMC_H 166564#define SRST_SFC_H 167565#define SRST_SFCXIP_H 168566#define SRST_SFC 169567#define SRST_NANDC_H 170568#define SRST_NANDC 171569#define SRST_PDSDMMC_H 173570#define SRST_PDSDIO_H 174571 572/* cru_softrst_con11 */573#define SRST_PDUSB_NIU_A 176574#define SRST_PDUSB_NIU_H 177575#define SRST_USBHOST_H 178576#define SRST_USBHOST_ARB_H 179577#define SRST_USBHOST_UTMI 180578#define SRST_USBOTG_A 181579#define SRST_USBPHY_OTG_P 182580#define SRST_USBPHY_HOST_P 183581#define SRST_USBPHYPOR_OTG 184582#define SRST_USBPHYPOR_HOST 185583#define SRST_PDGMAC_NIU_A 188584#define SRST_PDGMAC_NIU_P 189585#define SRST_GMAC_A 190586 587/* cru_softrst_con12 */588#define SRST_DDR_DFICTL_P 193589#define SRST_DDR_MON_P 194590#define SRST_DDR_STANDBY_P 195591#define SRST_DDR_GRF_P 196592#define SRST_DDR_MSCH_P 197593#define SRST_DDR_SPLIT_A 198594#define SRST_DDR_MSCH 199595#define SRST_DDR_DFICTL 202596#define SRST_DDR_STANDBY 203597#define SRST_NPUMCU_NIU 205598#define SRST_DDRPHY_P 206599#define SRST_DDRPHY 207600 601/* cru_softrst_con13 */602#define SRST_PDNPU_NIU_A 208603#define SRST_PDNPU_NIU_H 209604#define SRST_PDNPU_NIU_P 210605#define SRST_NPU_A 211606#define SRST_NPU_H 212607#define SRST_NPU 213608#define SRST_NPUPVTM_P 214609#define SRST_NPUPVTM 215610#define SRST_NPU_TSADC_P 216611#define SRST_NPU_TSADC 217612#define SRST_NPU_TSADCPHY 218613#define SRST_CIFLITE_A 220614#define SRST_CIFLITE_H 221615#define SRST_CIFLITE_D 222616#define SRST_CIFLITE_RX_P 223617 618/* cru_softrst_con14 */619#define SRST_TOPNIU_P 224620#define SRST_TOPCRU_P 225621#define SRST_TOPGRF_P 226622#define SRST_CPUEMADET_P 227623#define SRST_CSIPHY0_P 228624#define SRST_CSIPHY1_P 229625#define SRST_DSIPHY_P 230626#define SRST_CPU_TSADC_P 232627#define SRST_CPU_TSADC 233628#define SRST_CPU_TSADCPHY 234629#define SRST_CPUPVTM_P 235630#define SRST_CPUPVTM 236631 632#endif633