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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.4 * Author: Shawn Lin <shawn.lin@rock-chips.com>5 */6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H8#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H9 10/* pll id */11#define PLL_APLL 012#define PLL_DPLL 113#define PLL_GPLL 214#define ARMCLK 315 16/* sclk gates (special clocks) */17#define SCLK_SPI0 6518#define SCLK_NANDC 6719#define SCLK_SDMMC 6820#define SCLK_SDIO 6921#define SCLK_EMMC 7122#define SCLK_UART0 7223#define SCLK_UART1 7324#define SCLK_UART2 7425#define SCLK_I2S0 7526#define SCLK_I2S1 7627#define SCLK_I2S2 7728#define SCLK_TIMER0 7829#define SCLK_TIMER1 7930#define SCLK_SFC 8031#define SCLK_SDMMC_DRV 8132#define SCLK_SDIO_DRV 8233#define SCLK_EMMC_DRV 8334#define SCLK_SDMMC_SAMPLE 8435#define SCLK_SDIO_SAMPLE 8536#define SCLK_EMMC_SAMPLE 8637#define SCLK_VENC_CORE 8738#define SCLK_HEVC_CORE 8839#define SCLK_HEVC_CABAC 8940#define SCLK_PWM0_PMU 9041#define SCLK_I2C0_PMU 9142#define SCLK_WIFI 9243#define SCLK_CIFOUT 9344#define SCLK_MIPI_CSI_OUT 9445#define SCLK_CIF0 9546#define SCLK_CIF1 9647#define SCLK_CIF2 9748#define SCLK_CIF3 9849#define SCLK_DSP 9950#define SCLK_DSP_IOP 10051#define SCLK_DSP_EPP 10152#define SCLK_DSP_EDP 10253#define SCLK_DSP_EDAP 10354#define SCLK_CVBS_HOST 10455#define SCLK_HDMI_SFR 10556#define SCLK_HDMI_CEC 10657#define SCLK_CRYPTO 10758#define SCLK_SPI 10859#define SCLK_SARADC 10960#define SCLK_TSADC 11061#define SCLK_MAC_PRE 11162#define SCLK_MAC 11263#define SCLK_MAC_RX 11364#define SCLK_MAC_REF 11465#define SCLK_MAC_REFOUT 11566#define SCLK_DSP_PFM 11667#define SCLK_RGA 11768#define SCLK_I2C1 11869#define SCLK_I2C2 11970#define SCLK_I2C3 12071#define SCLK_PWM 12172#define SCLK_ISP 12273#define SCLK_USBPHY 12374#define SCLK_I2S0_SRC 12475#define SCLK_I2S1_SRC 12576#define SCLK_I2S2_SRC 12677#define SCLK_UART0_SRC 12778#define SCLK_UART1_SRC 12879#define SCLK_UART2_SRC 12980 81#define DCLK_VOP_SRC 18582#define DCLK_HDMIPHY 18683#define DCLK_VOP 18784 85/* aclk gates */86#define ACLK_DMAC 19287#define ACLK_PRE 19388#define ACLK_CORE 19489#define ACLK_ENMCORE 19590#define ACLK_RKVENC 19691#define ACLK_RKVDEC 19792#define ACLK_VPU 19893#define ACLK_CIF0 19994#define ACLK_VIO0 20095#define ACLK_VIO1 20196#define ACLK_VOP 20297#define ACLK_IEP 20398#define ACLK_RGA 20499#define ACLK_ISP 205100#define ACLK_CIF1 206101#define ACLK_CIF2 207102#define ACLK_CIF3 208103#define ACLK_PERI 209104#define ACLK_GMAC 210105 106/* pclk gates */107#define PCLK_GPIO1 256108#define PCLK_GPIO2 257109#define PCLK_GPIO3 258110#define PCLK_GRF 259111#define PCLK_I2C1 260112#define PCLK_I2C2 261113#define PCLK_I2C3 262114#define PCLK_SPI 263115#define PCLK_SFC 264116#define PCLK_UART0 265117#define PCLK_UART1 266118#define PCLK_UART2 267119#define PCLK_TSADC 268120#define PCLK_PWM 269121#define PCLK_TIMER 270122#define PCLK_PERI 271123#define PCLK_GPIO0_PMU 272124#define PCLK_I2C0_PMU 273125#define PCLK_PWM0_PMU 274126#define PCLK_ISP 275127#define PCLK_VIO 276128#define PCLK_MIPI_DSI 277129#define PCLK_HDMI_CTRL 278130#define PCLK_SARADC 279131#define PCLK_DSP_CFG 280132#define PCLK_BUS 281133#define PCLK_EFUSE0 282134#define PCLK_EFUSE1 283135#define PCLK_WDT 284136#define PCLK_GMAC 285137 138/* hclk gates */139#define HCLK_I2S0_8CH 320140#define HCLK_I2S1_2CH 321141#define HCLK_I2S2_2CH 322142#define HCLK_NANDC 323143#define HCLK_SDMMC 324144#define HCLK_SDIO 325145#define HCLK_EMMC 326146#define HCLK_PERI 327147#define HCLK_SFC 328148#define HCLK_RKVENC 329149#define HCLK_RKVDEC 330150#define HCLK_CIF0 331151#define HCLK_VIO 332152#define HCLK_VOP 333153#define HCLK_IEP 334154#define HCLK_RGA 335155#define HCLK_ISP 336156#define HCLK_CRYPTO_MST 337157#define HCLK_CRYPTO_SLV 338158#define HCLK_HOST0 339159#define HCLK_OTG 340160#define HCLK_CIF1 341161#define HCLK_CIF2 342162#define HCLK_CIF3 343163#define HCLK_BUS 344164#define HCLK_VPU 345165 166#define CLK_NR_CLKS (HCLK_VPU + 1)167 168/* reset id */169#define SRST_CORE_PO_AD 0170#define SRST_CORE_AD 1171#define SRST_L2_AD 2172#define SRST_CPU_NIU_AD 3173#define SRST_CORE_PO 4174#define SRST_CORE 5175#define SRST_L2 6176#define SRST_CORE_DBG 8177#define PRST_DBG 9178#define RST_DAP 10179#define PRST_DBG_NIU 11180#define ARST_STRC_SYS_AD 15181 182#define SRST_DDRPHY_CLKDIV 16183#define SRST_DDRPHY 17184#define PRST_DDRPHY 18185#define PRST_HDMIPHY 19186#define PRST_VDACPHY 20187#define PRST_VADCPHY 21188#define PRST_MIPI_CSI_PHY 22189#define PRST_MIPI_DSI_PHY 23190#define PRST_ACODEC 24191#define ARST_BUS_NIU 25192#define PRST_TOP_NIU 26193#define ARST_INTMEM 27194#define HRST_ROM 28195#define ARST_DMAC 29196#define SRST_MSCH_NIU 30197#define PRST_MSCH_NIU 31198 199#define PRST_DDRUPCTL 32200#define NRST_DDRUPCTL 33201#define PRST_DDRMON 34202#define HRST_I2S0_8CH 35203#define MRST_I2S0_8CH 36204#define HRST_I2S1_2CH 37205#define MRST_IS21_2CH 38206#define HRST_I2S2_2CH 39207#define MRST_I2S2_2CH 40208#define HRST_CRYPTO 41209#define SRST_CRYPTO 42210#define PRST_SPI 43211#define SRST_SPI 44212#define PRST_UART0 45213#define PRST_UART1 46214#define PRST_UART2 47215 216#define SRST_UART0 48217#define SRST_UART1 49218#define SRST_UART2 50219#define PRST_I2C1 51220#define PRST_I2C2 52221#define PRST_I2C3 53222#define SRST_I2C1 54223#define SRST_I2C2 55224#define SRST_I2C3 56225#define PRST_PWM1 58226#define SRST_PWM1 60227#define PRST_WDT 61228#define PRST_GPIO1 62229#define PRST_GPIO2 63230 231#define PRST_GPIO3 64232#define PRST_GRF 65233#define PRST_EFUSE 66234#define PRST_EFUSE512 67235#define PRST_TIMER0 68236#define SRST_TIMER0 69237#define SRST_TIMER1 70238#define PRST_TSADC 71239#define SRST_TSADC 72240#define PRST_SARADC 73241#define SRST_SARADC 74242#define HRST_SYSBUS 75243#define PRST_USBGRF 76244 245#define ARST_PERIPH_NIU 80246#define HRST_PERIPH_NIU 81247#define PRST_PERIPH_NIU 82248#define HRST_PERIPH 83249#define HRST_SDMMC 84250#define HRST_SDIO 85251#define HRST_EMMC 86252#define HRST_NANDC 87253#define NRST_NANDC 88254#define HRST_SFC 89255#define SRST_SFC 90256#define ARST_GMAC 91257#define HRST_OTG 92258#define SRST_OTG 93259#define SRST_OTG_ADP 94260#define HRST_HOST0 95261 262#define HRST_HOST0_AUX 96263#define HRST_HOST0_ARB 97264#define SRST_HOST0_EHCIPHY 98265#define SRST_HOST0_UTMI 99266#define SRST_USBPOR 100267#define SRST_UTMI0 101268#define SRST_UTMI1 102269 270#define ARST_VIO0_NIU 102271#define ARST_VIO1_NIU 103272#define HRST_VIO_NIU 104273#define PRST_VIO_NIU 105274#define ARST_VOP 106275#define HRST_VOP 107276#define DRST_VOP 108277#define ARST_IEP 109278#define HRST_IEP 110279#define ARST_RGA 111280#define HRST_RGA 112281#define SRST_RGA 113282#define PRST_CVBS 114283#define PRST_HDMI 115284#define SRST_HDMI 116285#define PRST_MIPI_DSI 117286 287#define ARST_ISP_NIU 118288#define HRST_ISP_NIU 119289#define HRST_ISP 120290#define SRST_ISP 121291#define ARST_VIP0 122292#define HRST_VIP0 123293#define PRST_VIP0 124294#define ARST_VIP1 125295#define HRST_VIP1 126296#define PRST_VIP1 127297#define ARST_VIP2 128298#define HRST_VIP2 129299#define PRST_VIP2 120300#define ARST_VIP3 121301#define HRST_VIP3 122302#define PRST_VIP4 123303 304#define PRST_CIF1TO4 124305#define SRST_CVBS_CLK 125306#define HRST_CVBS 126307 308#define ARST_VPU_NIU 140309#define HRST_VPU_NIU 141310#define ARST_VPU 142311#define HRST_VPU 143312#define ARST_RKVDEC_NIU 144313#define HRST_RKVDEC_NIU 145314#define ARST_RKVDEC 146315#define HRST_RKVDEC 147316#define SRST_RKVDEC_CABAC 148317#define SRST_RKVDEC_CORE 149318#define ARST_RKVENC_NIU 150319#define HRST_RKVENC_NIU 151320#define ARST_RKVENC 152321#define HRST_RKVENC 153322#define SRST_RKVENC_CORE 154323 324#define SRST_DSP_CORE 156325#define SRST_DSP_SYS 157326#define SRST_DSP_GLOBAL 158327#define SRST_DSP_OECM 159328#define PRST_DSP_IOP_NIU 160329#define ARST_DSP_EPP_NIU 161330#define ARST_DSP_EDP_NIU 162331#define PRST_DSP_DBG_NIU 163332#define PRST_DSP_CFG_NIU 164333#define PRST_DSP_GRF 165334#define PRST_DSP_MAILBOX 166335#define PRST_DSP_INTC 167336#define PRST_DSP_PFM_MON 169337#define SRST_DSP_PFM_MON 170338#define ARST_DSP_EDAP_NIU 171339 340#define SRST_PMU 172341#define SRST_PMU_I2C0 173342#define PRST_PMU_I2C0 174343#define PRST_PMU_GPIO0 175344#define PRST_PMU_INTMEM 176345#define PRST_PMU_PWM0 177346#define SRST_PMU_PWM0 178347#define PRST_PMU_GRF 179348#define SRST_PMU_NIU 180349#define SRST_PMU_PVTM 181350#define ARST_DSP_EDP_PERF 184351#define ARST_DSP_EPP_PERF 185352 353#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */354