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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.4 * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>5 *6 * Device Tree binding constants for Samsung S5PV210 clock controller.7 */8 9#ifndef _DT_BINDINGS_CLOCK_S5PV210_H10#define _DT_BINDINGS_CLOCK_S5PV210_H11 12/* Core clocks. */13#define FIN_PLL 114#define FOUT_APLL 215#define FOUT_MPLL 316#define FOUT_EPLL 417#define FOUT_VPLL 518 19/* Muxes. */20#define MOUT_FLASH 621#define MOUT_PSYS 722#define MOUT_DSYS 823#define MOUT_MSYS 924#define MOUT_VPLL 1025#define MOUT_EPLL 1126#define MOUT_MPLL 1227#define MOUT_APLL 1328#define MOUT_VPLLSRC 1429#define MOUT_CSIS 1530#define MOUT_FIMD 1631#define MOUT_CAM1 1732#define MOUT_CAM0 1833#define MOUT_DAC 1934#define MOUT_MIXER 2035#define MOUT_HDMI 2136#define MOUT_G2D 2237#define MOUT_MFC 2338#define MOUT_G3D 2439#define MOUT_FIMC2 2540#define MOUT_FIMC1 2641#define MOUT_FIMC0 2742#define MOUT_UART3 2843#define MOUT_UART2 2944#define MOUT_UART1 3045#define MOUT_UART0 3146#define MOUT_MMC3 3247#define MOUT_MMC2 3348#define MOUT_MMC1 3449#define MOUT_MMC0 3550#define MOUT_PWM 3651#define MOUT_SPI0 3752#define MOUT_SPI1 3853#define MOUT_DMC0 3954#define MOUT_PWI 4055#define MOUT_HPM 4156#define MOUT_SPDIF 4257#define MOUT_AUDIO2 4358#define MOUT_AUDIO1 4459#define MOUT_AUDIO0 4560 61/* Dividers. */62#define DOUT_PCLKP 4663#define DOUT_HCLKP 4764#define DOUT_PCLKD 4865#define DOUT_HCLKD 4966#define DOUT_PCLKM 5067#define DOUT_HCLKM 5168#define DOUT_A2M 5269#define DOUT_APLL 5370#define DOUT_CSIS 5471#define DOUT_FIMD 5572#define DOUT_CAM1 5673#define DOUT_CAM0 5774#define DOUT_TBLK 5875#define DOUT_G2D 5976#define DOUT_MFC 6077#define DOUT_G3D 6178#define DOUT_FIMC2 6279#define DOUT_FIMC1 6380#define DOUT_FIMC0 6481#define DOUT_UART3 6582#define DOUT_UART2 6683#define DOUT_UART1 6784#define DOUT_UART0 6885#define DOUT_MMC3 6986#define DOUT_MMC2 7087#define DOUT_MMC1 7188#define DOUT_MMC0 7289#define DOUT_PWM 7390#define DOUT_SPI1 7491#define DOUT_SPI0 7592#define DOUT_DMC0 7693#define DOUT_PWI 7794#define DOUT_HPM 7895#define DOUT_COPY 7996#define DOUT_FLASH 8097#define DOUT_AUDIO2 8198#define DOUT_AUDIO1 8299#define DOUT_AUDIO0 83100#define DOUT_DPM 84101#define DOUT_DVSEM 85102 103/* Gates */104#define SCLK_FIMC 86105#define CLK_CSIS 87106#define CLK_ROTATOR 88107#define CLK_FIMC2 89108#define CLK_FIMC1 90109#define CLK_FIMC0 91110#define CLK_MFC 92111#define CLK_G2D 93112#define CLK_G3D 94113#define CLK_IMEM 95114#define CLK_PDMA1 96115#define CLK_PDMA0 97116#define CLK_MDMA 98117#define CLK_DMC1 99118#define CLK_DMC0 100119#define CLK_NFCON 101120#define CLK_SROMC 102121#define CLK_CFCON 103122#define CLK_NANDXL 104123#define CLK_USB_HOST 105124#define CLK_USB_OTG 106125#define CLK_HDMI 107126#define CLK_TVENC 108127#define CLK_MIXER 109128#define CLK_VP 110129#define CLK_DSIM 111130#define CLK_FIMD 112131#define CLK_TZIC3 113132#define CLK_TZIC2 114133#define CLK_TZIC1 115134#define CLK_TZIC0 116135#define CLK_VIC3 117136#define CLK_VIC2 118137#define CLK_VIC1 119138#define CLK_VIC0 120139#define CLK_TSI 121140#define CLK_HSMMC3 122141#define CLK_HSMMC2 123142#define CLK_HSMMC1 124143#define CLK_HSMMC0 125144#define CLK_JTAG 126145#define CLK_MODEMIF 127146#define CLK_CORESIGHT 128147#define CLK_SDM 129148#define CLK_SECSS 130149#define CLK_PCM2 131150#define CLK_PCM1 132151#define CLK_PCM0 133152#define CLK_SYSCON 134153#define CLK_GPIO 135154#define CLK_TSADC 136155#define CLK_PWM 137156#define CLK_WDT 138157#define CLK_KEYIF 139158#define CLK_UART3 140159#define CLK_UART2 141160#define CLK_UART1 142161#define CLK_UART0 143162#define CLK_SYSTIMER 144163#define CLK_RTC 145164#define CLK_SPI1 146165#define CLK_SPI0 147166#define CLK_I2C_HDMI_PHY 148167#define CLK_I2C1 149168#define CLK_I2C2 150169#define CLK_I2C0 151170#define CLK_I2S1 152171#define CLK_I2S2 153172#define CLK_I2S0 154173#define CLK_AC97 155174#define CLK_SPDIF 156175#define CLK_TZPC3 157176#define CLK_TZPC2 158177#define CLK_TZPC1 159178#define CLK_TZPC0 160179#define CLK_SECKEY 161180#define CLK_IEM_APC 162181#define CLK_IEM_IEC 163182#define CLK_CHIPID 164183#define CLK_JPEG 163184 185/* Special clocks*/186#define SCLK_PWI 164187#define SCLK_SPDIF 165188#define SCLK_AUDIO2 166189#define SCLK_AUDIO1 167190#define SCLK_AUDIO0 168191#define SCLK_PWM 169192#define SCLK_SPI1 170193#define SCLK_SPI0 171194#define SCLK_UART3 172195#define SCLK_UART2 173196#define SCLK_UART1 174197#define SCLK_UART0 175198#define SCLK_MMC3 176199#define SCLK_MMC2 177200#define SCLK_MMC1 178201#define SCLK_MMC0 179202#define SCLK_FINVPLL 180203#define SCLK_CSIS 181204#define SCLK_FIMD 182205#define SCLK_CAM1 183206#define SCLK_CAM0 184207#define SCLK_DAC 185208#define SCLK_MIXER 186209#define SCLK_HDMI 187210#define SCLK_FIMC2 188211#define SCLK_FIMC1 189212#define SCLK_FIMC0 190213#define SCLK_HDMI27M 191214#define SCLK_HDMIPHY 192215#define SCLK_USBPHY0 193216#define SCLK_USBPHY1 194217 218/* S5P6442-specific clocks */219#define MOUT_D0SYNC 195220#define MOUT_D1SYNC 196221#define DOUT_MIXER 197222#define CLK_ETB 198223#define CLK_ETM 199224 225/* CLKOUT */226#define FOUT_APLL_CLKOUT 200227#define FOUT_MPLL_CLKOUT 201228#define DOUT_APLL_CLKOUT 202229#define MOUT_CLKSEL 203230#define DOUT_CLKOUT 204231#define MOUT_CLKOUT 205232 233/* Total number of clocks. */234#define NR_CLKS 206235 236#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */237