112 lines · c
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */2/*3 * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.4 */5 6#ifndef __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__7#define __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__8 9#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 010#define DIV_CLK_MPLL_AXI_DDR_0 111#define DIV_CLK_FPLL_DDR01_1 212#define DIV_CLK_FPLL_DDR23_1 313#define DIV_CLK_FPLL_RP_CPU_NORMAL_1 414#define DIV_CLK_FPLL_50M_A53 515#define DIV_CLK_FPLL_TOP_RP_CMN_DIV2 616#define DIV_CLK_FPLL_UART_500M 717#define DIV_CLK_FPLL_AHB_LPC 818#define DIV_CLK_FPLL_EFUSE 919#define DIV_CLK_FPLL_TX_ETH0 1020#define DIV_CLK_FPLL_PTP_REF_I_ETH0 1121#define DIV_CLK_FPLL_REF_ETH0 1222#define DIV_CLK_FPLL_EMMC 1323#define DIV_CLK_FPLL_SD 1424#define DIV_CLK_FPLL_TOP_AXI0 1525#define DIV_CLK_FPLL_TOP_AXI_HSPERI 1626#define DIV_CLK_FPLL_AXI_DDR_1 1727#define DIV_CLK_FPLL_DIV_TIMER1 1828#define DIV_CLK_FPLL_DIV_TIMER2 1929#define DIV_CLK_FPLL_DIV_TIMER3 2030#define DIV_CLK_FPLL_DIV_TIMER4 2131#define DIV_CLK_FPLL_DIV_TIMER5 2232#define DIV_CLK_FPLL_DIV_TIMER6 2333#define DIV_CLK_FPLL_DIV_TIMER7 2434#define DIV_CLK_FPLL_DIV_TIMER8 2535#define DIV_CLK_FPLL_100K_EMMC 2636#define DIV_CLK_FPLL_100K_SD 2737#define DIV_CLK_FPLL_GPIO_DB 2838#define DIV_CLK_DPLL0_DDR01_0 2939#define DIV_CLK_DPLL1_DDR23_0 3040 41#define GATE_CLK_RP_CPU_NORMAL_DIV0 3142#define GATE_CLK_AXI_DDR_DIV0 3243 44#define GATE_CLK_RP_CPU_NORMAL_DIV1 3345#define GATE_CLK_A53_50M 3446#define GATE_CLK_TOP_RP_CMN_DIV2 3547#define GATE_CLK_HSDMA 3648#define GATE_CLK_EMMC_100M 3749#define GATE_CLK_SD_100M 3850#define GATE_CLK_TX_ETH0 3951#define GATE_CLK_PTP_REF_I_ETH0 4052#define GATE_CLK_REF_ETH0 4153#define GATE_CLK_UART_500M 4254#define GATE_CLK_EFUSE 4355 56#define GATE_CLK_AHB_LPC 4457#define GATE_CLK_AHB_ROM 4558#define GATE_CLK_AHB_SF 4659 60#define GATE_CLK_APB_UART 4761#define GATE_CLK_APB_TIMER 4862#define GATE_CLK_APB_EFUSE 4963#define GATE_CLK_APB_GPIO 5064#define GATE_CLK_APB_GPIO_INTR 5165#define GATE_CLK_APB_SPI 5266#define GATE_CLK_APB_I2C 5367#define GATE_CLK_APB_WDT 5468#define GATE_CLK_APB_PWM 5569#define GATE_CLK_APB_RTC 5670 71#define GATE_CLK_AXI_PCIE0 5772#define GATE_CLK_AXI_PCIE1 5873#define GATE_CLK_SYSDMA_AXI 5974#define GATE_CLK_AXI_DBG_I2C 6075#define GATE_CLK_AXI_SRAM 6176#define GATE_CLK_AXI_ETH0 6277#define GATE_CLK_AXI_EMMC 6378#define GATE_CLK_AXI_SD 6479#define GATE_CLK_TOP_AXI0 6580#define GATE_CLK_TOP_AXI_HSPERI 6681 82#define GATE_CLK_TIMER1 6783#define GATE_CLK_TIMER2 6884#define GATE_CLK_TIMER3 6985#define GATE_CLK_TIMER4 7086#define GATE_CLK_TIMER5 7187#define GATE_CLK_TIMER6 7288#define GATE_CLK_TIMER7 7389#define GATE_CLK_TIMER8 7490#define GATE_CLK_100K_EMMC 7591#define GATE_CLK_100K_SD 7692#define GATE_CLK_GPIO_DB 7793 94#define GATE_CLK_AXI_DDR_DIV1 7895#define GATE_CLK_DDR01_DIV1 7996#define GATE_CLK_DDR23_DIV1 8097 98#define GATE_CLK_DDR01_DIV0 8199#define GATE_CLK_DDR23_DIV0 82100 101#define GATE_CLK_DDR01 83102#define GATE_CLK_DDR23 84103#define GATE_CLK_RP_CPU_NORMAL 85104#define GATE_CLK_AXI_DDR 86105 106#define MUX_CLK_DDR01 87107#define MUX_CLK_DDR23 88108#define MUX_CLK_RP_CPU_NORMAL 89109#define MUX_CLK_AXI_DDR 90110 111#endif /* __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ */112