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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)2//3// Spreadtrum SC9860 platform clocks4//5// Copyright (C) 2017, Spreadtrum Communications Inc.6 7#ifndef _DT_BINDINGS_CLK_SC9860_H_8#define _DT_BINDINGS_CLK_SC9860_H_9 10#define CLK_FAC_4M 011#define CLK_FAC_2M 112#define CLK_FAC_1M 213#define CLK_FAC_250K 314#define CLK_FAC_RPLL0_26M 415#define CLK_FAC_RPLL1_26M 516#define CLK_FAC_RCO25M 617#define CLK_FAC_RCO4M 718#define CLK_FAC_RCO2M 819#define CLK_FAC_3K2 920#define CLK_FAC_1K 1021#define CLK_MPLL0_GATE 1122#define CLK_MPLL1_GATE 1223#define CLK_DPLL0_GATE 1324#define CLK_DPLL1_GATE 1425#define CLK_LTEPLL0_GATE 1526#define CLK_TWPLL_GATE 1627#define CLK_LTEPLL1_GATE 1728#define CLK_RPLL0_GATE 1829#define CLK_RPLL1_GATE 1930#define CLK_CPPLL_GATE 2031#define CLK_GPLL_GATE 2132#define CLK_PMU_GATE_NUM (CLK_GPLL_GATE + 1)33 34#define CLK_MPLL0 035#define CLK_MPLL1 136#define CLK_DPLL0 237#define CLK_DPLL1 338#define CLK_RPLL0 439#define CLK_RPLL1 540#define CLK_TWPLL 641#define CLK_LTEPLL0 742#define CLK_LTEPLL1 843#define CLK_GPLL 944#define CLK_CPPLL 1045#define CLK_GPLL_42M5 1146#define CLK_TWPLL_768M 1247#define CLK_TWPLL_384M 1348#define CLK_TWPLL_192M 1449#define CLK_TWPLL_96M 1550#define CLK_TWPLL_48M 1651#define CLK_TWPLL_24M 1752#define CLK_TWPLL_12M 1853#define CLK_TWPLL_512M 1954#define CLK_TWPLL_256M 2055#define CLK_TWPLL_128M 2156#define CLK_TWPLL_64M 2257#define CLK_TWPLL_307M2 2358#define CLK_TWPLL_153M6 2459#define CLK_TWPLL_76M8 2560#define CLK_TWPLL_51M2 2661#define CLK_TWPLL_38M4 2762#define CLK_TWPLL_19M2 2863#define CLK_L0_614M4 2964#define CLK_L0_409M6 3065#define CLK_L0_38M 3166#define CLK_L1_38M 3267#define CLK_RPLL0_192M 3368#define CLK_RPLL0_96M 3469#define CLK_RPLL0_48M 3570#define CLK_RPLL1_468M 3671#define CLK_RPLL1_192M 3772#define CLK_RPLL1_96M 3873#define CLK_RPLL1_64M 3974#define CLK_RPLL1_48M 4075#define CLK_DPLL0_50M 4176#define CLK_DPLL1_50M 4277#define CLK_CPPLL_50M 4378#define CLK_M0_39M 4479#define CLK_M1_63M 4580#define CLK_PLL_NUM (CLK_M1_63M + 1)81 82 83#define CLK_AP_APB 084#define CLK_AP_USB3 185#define CLK_UART0 286#define CLK_UART1 387#define CLK_UART2 488#define CLK_UART3 589#define CLK_UART4 690#define CLK_I2C0 791#define CLK_I2C1 892#define CLK_I2C2 993#define CLK_I2C3 1094#define CLK_I2C4 1195#define CLK_I2C5 1296#define CLK_SPI0 1397#define CLK_SPI1 1498#define CLK_SPI2 1599#define CLK_SPI3 16100#define CLK_IIS0 17101#define CLK_IIS1 18102#define CLK_IIS2 19103#define CLK_IIS3 20104#define CLK_AP_CLK_NUM (CLK_IIS3 + 1)105 106#define CLK_AON_APB 0107#define CLK_AUX0 1108#define CLK_AUX1 2109#define CLK_AUX2 3110#define CLK_PROBE 4111#define CLK_SP_AHB 5112#define CLK_CCI 6113#define CLK_GIC 7114#define CLK_CSSYS 8115#define CLK_SDIO0_2X 9116#define CLK_SDIO1_2X 10117#define CLK_SDIO2_2X 11118#define CLK_EMMC_2X 12119#define CLK_SDIO0_1X 13120#define CLK_SDIO1_1X 14121#define CLK_SDIO2_1X 15122#define CLK_EMMC_1X 16123#define CLK_ADI 17124#define CLK_PWM0 18125#define CLK_PWM1 19126#define CLK_PWM2 20127#define CLK_PWM3 21128#define CLK_EFUSE 22129#define CLK_CM3_UART0 23130#define CLK_CM3_UART1 24131#define CLK_THM 25132#define CLK_CM3_I2C0 26133#define CLK_CM3_I2C1 27134#define CLK_CM4_SPI 28135#define CLK_AON_I2C 29136#define CLK_AVS 30137#define CLK_CA53_DAP 31138#define CLK_CA53_TS 32139#define CLK_DJTAG_TCK 33140#define CLK_PMU 34141#define CLK_PMU_26M 35142#define CLK_DEBOUNCE 36143#define CLK_OTG2_REF 37144#define CLK_USB3_REF 38145#define CLK_AP_AXI 39146#define CLK_AON_PREDIV_NUM (CLK_AP_AXI + 1)147 148#define CLK_USB3_EB 0149#define CLK_USB3_SUSPEND_EB 1150#define CLK_USB3_REF_EB 2151#define CLK_DMA_EB 3152#define CLK_SDIO0_EB 4153#define CLK_SDIO1_EB 5154#define CLK_SDIO2_EB 6155#define CLK_EMMC_EB 7156#define CLK_ROM_EB 8157#define CLK_BUSMON_EB 9158#define CLK_CC63S_EB 10159#define CLK_CC63P_EB 11160#define CLK_CE0_EB 12161#define CLK_CE1_EB 13162#define CLK_APAHB_GATE_NUM (CLK_CE1_EB + 1)163 164#define CLK_AVS_LIT_EB 0165#define CLK_AVS_BIG_EB 1166#define CLK_AP_INTC5_EB 2167#define CLK_GPIO_EB 3168#define CLK_PWM0_EB 4169#define CLK_PWM1_EB 5170#define CLK_PWM2_EB 6171#define CLK_PWM3_EB 7172#define CLK_KPD_EB 8173#define CLK_AON_SYS_EB 9174#define CLK_AP_SYS_EB 10175#define CLK_AON_TMR_EB 11176#define CLK_AP_TMR0_EB 12177#define CLK_EFUSE_EB 13178#define CLK_EIC_EB 14179#define CLK_PUB1_REG_EB 15180#define CLK_ADI_EB 16181#define CLK_AP_INTC0_EB 17182#define CLK_AP_INTC1_EB 18183#define CLK_AP_INTC2_EB 19184#define CLK_AP_INTC3_EB 20185#define CLK_AP_INTC4_EB 21186#define CLK_SPLK_EB 22187#define CLK_MSPI_EB 23188#define CLK_PUB0_REG_EB 24189#define CLK_PIN_EB 25190#define CLK_AON_CKG_EB 26191#define CLK_GPU_EB 27192#define CLK_APCPU_TS0_EB 28193#define CLK_APCPU_TS1_EB 29194#define CLK_DAP_EB 30195#define CLK_I2C_EB 31196#define CLK_PMU_EB 32197#define CLK_THM_EB 33198#define CLK_AUX0_EB 34199#define CLK_AUX1_EB 35200#define CLK_AUX2_EB 36201#define CLK_PROBE_EB 37202#define CLK_GPU0_AVS_EB 38203#define CLK_GPU1_AVS_EB 39204#define CLK_APCPU_WDG_EB 40205#define CLK_AP_TMR1_EB 41206#define CLK_AP_TMR2_EB 42207#define CLK_DISP_EMC_EB 43208#define CLK_ZIP_EMC_EB 44209#define CLK_GSP_EMC_EB 45210#define CLK_OSC_AON_EB 46211#define CLK_LVDS_TRX_EB 47212#define CLK_LVDS_TCXO_EB 48213#define CLK_MDAR_EB 49214#define CLK_RTC4M0_CAL_EB 50215#define CLK_RCT100M_CAL_EB 51216#define CLK_DJTAG_EB 52217#define CLK_MBOX_EB 53218#define CLK_AON_DMA_EB 54219#define CLK_DBG_EMC_EB 55220#define CLK_LVDS_PLL_DIV_EN 56221#define CLK_DEF_EB 57222#define CLK_AON_APB_RSV0 58223#define CLK_ORP_JTAG_EB 59224#define CLK_VSP_EB 60225#define CLK_CAM_EB 61226#define CLK_DISP_EB 62227#define CLK_DBG_AXI_IF_EB 63228#define CLK_SDIO0_2X_EN 64229#define CLK_SDIO1_2X_EN 65230#define CLK_SDIO2_2X_EN 66231#define CLK_EMMC_2X_EN 67232#define CLK_ARCH_RTC_EB 68233#define CLK_KPB_RTC_EB 69234#define CLK_AON_SYST_RTC_EB 70235#define CLK_AP_SYST_RTC_EB 71236#define CLK_AON_TMR_RTC_EB 72237#define CLK_AP_TMR0_RTC_EB 73238#define CLK_EIC_RTC_EB 74239#define CLK_EIC_RTCDV5_EB 75240#define CLK_AP_WDG_RTC_EB 76241#define CLK_AP_TMR1_RTC_EB 77242#define CLK_AP_TMR2_RTC_EB 78243#define CLK_DCXO_TMR_RTC_EB 79244#define CLK_BB_CAL_RTC_EB 80245#define CLK_AVS_BIG_RTC_EB 81246#define CLK_AVS_LIT_RTC_EB 82247#define CLK_AVS_GPU0_RTC_EB 83248#define CLK_AVS_GPU1_RTC_EB 84249#define CLK_GPU_TS_EB 85250#define CLK_RTCDV10_EB 86251#define CLK_AON_GATE_NUM (CLK_RTCDV10_EB + 1)252 253#define CLK_LIT_MCU 0254#define CLK_BIG_MCU 1255#define CLK_AONSECURE_NUM (CLK_BIG_MCU + 1)256 257#define CLK_AGCP_IIS0_EB 0258#define CLK_AGCP_IIS1_EB 1259#define CLK_AGCP_IIS2_EB 2260#define CLK_AGCP_IIS3_EB 3261#define CLK_AGCP_UART_EB 4262#define CLK_AGCP_DMACP_EB 5263#define CLK_AGCP_DMAAP_EB 6264#define CLK_AGCP_ARC48K_EB 7265#define CLK_AGCP_SRC44P1K_EB 8266#define CLK_AGCP_MCDT_EB 9267#define CLK_AGCP_VBCIFD_EB 10268#define CLK_AGCP_VBC_EB 11269#define CLK_AGCP_SPINLOCK_EB 12270#define CLK_AGCP_ICU_EB 13271#define CLK_AGCP_AP_ASHB_EB 14272#define CLK_AGCP_CP_ASHB_EB 15273#define CLK_AGCP_AUD_EB 16274#define CLK_AGCP_AUDIF_EB 17275#define CLK_AGCP_GATE_NUM (CLK_AGCP_AUDIF_EB + 1)276 277#define CLK_GPU 0278#define CLK_GPU_NUM (CLK_GPU + 1)279 280#define CLK_AHB_VSP 0281#define CLK_VSP 1282#define CLK_VSP_ENC 2283#define CLK_VPP 3284#define CLK_VSP_26M 4285#define CLK_VSP_NUM (CLK_VSP_26M + 1)286 287#define CLK_VSP_DEC_EB 0288#define CLK_VSP_CKG_EB 1289#define CLK_VSP_MMU_EB 2290#define CLK_VSP_ENC_EB 3291#define CLK_VPP_EB 4292#define CLK_VSP_26M_EB 5293#define CLK_VSP_AXI_GATE 6294#define CLK_VSP_ENC_GATE 7295#define CLK_VPP_AXI_GATE 8296#define CLK_VSP_BM_GATE 9297#define CLK_VSP_ENC_BM_GATE 10298#define CLK_VPP_BM_GATE 11299#define CLK_VSP_GATE_NUM (CLK_VPP_BM_GATE + 1)300 301#define CLK_AHB_CAM 0302#define CLK_SENSOR0 1303#define CLK_SENSOR1 2304#define CLK_SENSOR2 3305#define CLK_MIPI_CSI0_EB 4306#define CLK_MIPI_CSI1_EB 5307#define CLK_CAM_NUM (CLK_MIPI_CSI1_EB + 1)308 309#define CLK_DCAM0_EB 0310#define CLK_DCAM1_EB 1311#define CLK_ISP0_EB 2312#define CLK_CSI0_EB 3313#define CLK_CSI1_EB 4314#define CLK_JPG0_EB 5315#define CLK_JPG1_EB 6316#define CLK_CAM_CKG_EB 7317#define CLK_CAM_MMU_EB 8318#define CLK_ISP1_EB 9319#define CLK_CPP_EB 10320#define CLK_MMU_PF_EB 11321#define CLK_ISP2_EB 12322#define CLK_DCAM2ISP_IF_EB 13323#define CLK_ISP2DCAM_IF_EB 14324#define CLK_ISP_LCLK_EB 15325#define CLK_ISP_ICLK_EB 16326#define CLK_ISP_MCLK_EB 17327#define CLK_ISP_PCLK_EB 18328#define CLK_ISP_ISP2DCAM_EB 19329#define CLK_DCAM0_IF_EB 20330#define CLK_CLK26M_IF_EB 21331#define CLK_CPHY0_GATE 22332#define CLK_MIPI_CSI0_GATE 23333#define CLK_CPHY1_GATE 24334#define CLK_MIPI_CSI1 25335#define CLK_DCAM0_AXI_GATE 26336#define CLK_DCAM1_AXI_GATE 27337#define CLK_SENSOR0_GATE 28338#define CLK_SENSOR1_GATE 29339#define CLK_JPG0_AXI_GATE 30340#define CLK_GPG1_AXI_GATE 31341#define CLK_ISP0_AXI_GATE 32342#define CLK_ISP1_AXI_GATE 33343#define CLK_ISP2_AXI_GATE 34344#define CLK_CPP_AXI_GATE 35345#define CLK_D0_IF_AXI_GATE 36346#define CLK_D2I_IF_AXI_GATE 37347#define CLK_I2D_IF_AXI_GATE 38348#define CLK_SPARE_AXI_GATE 39349#define CLK_SENSOR2_GATE 40350#define CLK_D0IF_IN_D_EN 41351#define CLK_D1IF_IN_D_EN 42352#define CLK_D0IF_IN_D2I_EN 43353#define CLK_D1IF_IN_D2I_EN 44354#define CLK_IA_IN_D2I_EN 45355#define CLK_IB_IN_D2I_EN 46356#define CLK_IC_IN_D2I_EN 47357#define CLK_IA_IN_I_EN 48358#define CLK_IB_IN_I_EN 49359#define CLK_IC_IN_I_EN 50360#define CLK_CAM_GATE_NUM (CLK_IC_IN_I_EN + 1)361 362#define CLK_AHB_DISP 0363#define CLK_DISPC0_DPI 1364#define CLK_DISPC1_DPI 2365#define CLK_DISP_NUM (CLK_DISPC1_DPI + 1)366 367#define CLK_DISPC0_EB 0368#define CLK_DISPC1_EB 1369#define CLK_DISPC_MMU_EB 2370#define CLK_GSP0_EB 3371#define CLK_GSP1_EB 4372#define CLK_GSP0_MMU_EB 5373#define CLK_GSP1_MMU_EB 6374#define CLK_DSI0_EB 7375#define CLK_DSI1_EB 8376#define CLK_DISP_CKG_EB 9377#define CLK_DISP_GPU_EB 10378#define CLK_GPU_MTX_EB 11379#define CLK_GSP_MTX_EB 12380#define CLK_TMC_MTX_EB 13381#define CLK_DISPC_MTX_EB 14382#define CLK_DPHY0_GATE 15383#define CLK_DPHY1_GATE 16384#define CLK_GSP0_A_GATE 17385#define CLK_GSP1_A_GATE 18386#define CLK_GSP0_F_GATE 19387#define CLK_GSP1_F_GATE 20388#define CLK_D_MTX_F_GATE 21389#define CLK_D_MTX_A_GATE 22390#define CLK_D_NOC_F_GATE 23391#define CLK_D_NOC_A_GATE 24392#define CLK_GSP_MTX_F_GATE 25393#define CLK_GSP_MTX_A_GATE 26394#define CLK_GSP_NOC_F_GATE 27395#define CLK_GSP_NOC_A_GATE 28396#define CLK_DISPM0IDLE_GATE 29397#define CLK_GSPM0IDLE_GATE 30398#define CLK_DISP_GATE_NUM (CLK_GSPM0IDLE_GATE + 1)399 400#define CLK_SIM0_EB 0401#define CLK_IIS0_EB 1402#define CLK_IIS1_EB 2403#define CLK_IIS2_EB 3404#define CLK_IIS3_EB 4405#define CLK_SPI0_EB 5406#define CLK_SPI1_EB 6407#define CLK_SPI2_EB 7408#define CLK_I2C0_EB 8409#define CLK_I2C1_EB 9410#define CLK_I2C2_EB 10411#define CLK_I2C3_EB 11412#define CLK_I2C4_EB 12413#define CLK_I2C5_EB 13414#define CLK_UART0_EB 14415#define CLK_UART1_EB 15416#define CLK_UART2_EB 16417#define CLK_UART3_EB 17418#define CLK_UART4_EB 18419#define CLK_AP_CKG_EB 19420#define CLK_SPI3_EB 20421#define CLK_APAPB_GATE_NUM (CLK_SPI3_EB + 1)422 423#endif /* _DT_BINDINGS_CLK_SC9860_H_ */424