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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Unisoc SC9863A platform clocks4 *5 * Copyright (C) 2019, Unisoc Communications Inc.6 */7 8#ifndef _DT_BINDINGS_CLK_SC9863A_H_9#define _DT_BINDINGS_CLK_SC9863A_H_10 11#define CLK_MPLL0_GATE 012#define CLK_DPLL0_GATE 113#define CLK_LPLL_GATE 214#define CLK_GPLL_GATE 315#define CLK_DPLL1_GATE 416#define CLK_MPLL1_GATE 517#define CLK_MPLL2_GATE 618#define CLK_ISPPLL_GATE 719#define CLK_PMU_APB_NUM (CLK_ISPPLL_GATE + 1)20 21#define CLK_AUDIO_GATE 022#define CLK_RPLL 123#define CLK_RPLL_390M 224#define CLK_RPLL_260M 325#define CLK_RPLL_195M 426#define CLK_RPLL_26M 527#define CLK_ANLG_PHY_G5_NUM (CLK_RPLL_26M + 1)28 29#define CLK_TWPLL 030#define CLK_TWPLL_768M 131#define CLK_TWPLL_384M 232#define CLK_TWPLL_192M 333#define CLK_TWPLL_96M 434#define CLK_TWPLL_48M 535#define CLK_TWPLL_24M 636#define CLK_TWPLL_12M 737#define CLK_TWPLL_512M 838#define CLK_TWPLL_256M 939#define CLK_TWPLL_128M 1040#define CLK_TWPLL_64M 1141#define CLK_TWPLL_307M2 1242#define CLK_TWPLL_219M4 1343#define CLK_TWPLL_170M6 1444#define CLK_TWPLL_153M6 1545#define CLK_TWPLL_76M8 1646#define CLK_TWPLL_51M2 1747#define CLK_TWPLL_38M4 1848#define CLK_TWPLL_19M2 1949#define CLK_LPLL 2050#define CLK_LPLL_409M6 2151#define CLK_LPLL_245M76 2252#define CLK_GPLL 2353#define CLK_ISPPLL 2454#define CLK_ISPPLL_468M 2555#define CLK_ANLG_PHY_G1_NUM (CLK_ISPPLL_468M + 1)56 57#define CLK_DPLL0 058#define CLK_DPLL1 159#define CLK_DPLL0_933M 260#define CLK_DPLL0_622M3 361#define CLK_DPLL0_400M 462#define CLK_DPLL0_266M7 563#define CLK_DPLL0_123M1 664#define CLK_DPLL0_50M 765#define CLK_ANLG_PHY_G7_NUM (CLK_DPLL0_50M + 1)66 67#define CLK_MPLL0 068#define CLK_MPLL1 169#define CLK_MPLL2 270#define CLK_MPLL2_675M 371#define CLK_ANLG_PHY_G4_NUM (CLK_MPLL2_675M + 1)72 73#define CLK_AP_APB 074#define CLK_AP_CE 175#define CLK_NANDC_ECC 276#define CLK_NANDC_26M 377#define CLK_EMMC_32K 478#define CLK_SDIO0_32K 579#define CLK_SDIO1_32K 680#define CLK_SDIO2_32K 781#define CLK_OTG_UTMI 882#define CLK_AP_UART0 983#define CLK_AP_UART1 1084#define CLK_AP_UART2 1185#define CLK_AP_UART3 1286#define CLK_AP_UART4 1387#define CLK_AP_I2C0 1488#define CLK_AP_I2C1 1589#define CLK_AP_I2C2 1690#define CLK_AP_I2C3 1791#define CLK_AP_I2C4 1892#define CLK_AP_I2C5 1993#define CLK_AP_I2C6 2094#define CLK_AP_SPI0 2195#define CLK_AP_SPI1 2296#define CLK_AP_SPI2 2397#define CLK_AP_SPI3 2498#define CLK_AP_IIS0 2599#define CLK_AP_IIS1 26100#define CLK_AP_IIS2 27101#define CLK_SIM0 28102#define CLK_SIM0_32K 29103#define CLK_AP_CLK_NUM (CLK_SIM0_32K + 1)104 105#define CLK_13M 0106#define CLK_6M5 1107#define CLK_4M3 2108#define CLK_2M 3109#define CLK_250K 4110#define CLK_RCO_25M 5111#define CLK_RCO_4M 6112#define CLK_RCO_2M 7113#define CLK_EMC 8114#define CLK_AON_APB 9115#define CLK_ADI 10116#define CLK_AUX0 11117#define CLK_AUX1 12118#define CLK_AUX2 13119#define CLK_PROBE 14120#define CLK_PWM0 15121#define CLK_PWM1 16122#define CLK_PWM2 17123#define CLK_AON_THM 18124#define CLK_AUDIF 19125#define CLK_CPU_DAP 20126#define CLK_CPU_TS 21127#define CLK_DJTAG_TCK 22128#define CLK_EMC_REF 23129#define CLK_CSSYS 24130#define CLK_AON_PMU 25131#define CLK_PMU_26M 26132#define CLK_AON_TMR 27133#define CLK_POWER_CPU 28134#define CLK_AP_AXI 29135#define CLK_SDIO0_2X 30136#define CLK_SDIO1_2X 31137#define CLK_SDIO2_2X 32138#define CLK_EMMC_2X 33139#define CLK_DPU 34140#define CLK_DPU_DPI 35141#define CLK_OTG_REF 36142#define CLK_SDPHY_APB 37143#define CLK_ALG_IO_APB 38144#define CLK_GPU_CORE 39145#define CLK_GPU_SOC 40146#define CLK_MM_EMC 41147#define CLK_MM_AHB 42148#define CLK_BPC 43149#define CLK_DCAM_IF 44150#define CLK_ISP 45151#define CLK_JPG 46152#define CLK_CPP 47153#define CLK_SENSOR0 48154#define CLK_SENSOR1 49155#define CLK_SENSOR2 50156#define CLK_MM_VEMC 51157#define CLK_MM_VAHB 52158#define CLK_VSP 53159#define CLK_CORE0 54160#define CLK_CORE1 55161#define CLK_CORE2 56162#define CLK_CORE3 57163#define CLK_CORE4 58164#define CLK_CORE5 59165#define CLK_CORE6 60166#define CLK_CORE7 61167#define CLK_SCU 62168#define CLK_ACE 63169#define CLK_AXI_PERIPH 64170#define CLK_AXI_ACP 65171#define CLK_ATB 66172#define CLK_DEBUG_APB 67173#define CLK_GIC 68174#define CLK_PERIPH 69175#define CLK_AON_CLK_NUM (CLK_VSP + 1)176 177#define CLK_OTG_EB 0178#define CLK_DMA_EB 1179#define CLK_CE_EB 2180#define CLK_NANDC_EB 3181#define CLK_SDIO0_EB 4182#define CLK_SDIO1_EB 5183#define CLK_SDIO2_EB 6184#define CLK_EMMC_EB 7185#define CLK_EMMC_32K_EB 8186#define CLK_SDIO0_32K_EB 9187#define CLK_SDIO1_32K_EB 10188#define CLK_SDIO2_32K_EB 11189#define CLK_NANDC_26M_EB 12190#define CLK_DMA_EB2 13191#define CLK_CE_EB2 14192#define CLK_AP_AHB_GATE_NUM (CLK_CE_EB2 + 1)193 194#define CLK_GPIO_EB 0195#define CLK_PWM0_EB 1196#define CLK_PWM1_EB 2197#define CLK_PWM2_EB 3198#define CLK_PWM3_EB 4199#define CLK_KPD_EB 5200#define CLK_AON_SYST_EB 6201#define CLK_AP_SYST_EB 7202#define CLK_AON_TMR_EB 8203#define CLK_EFUSE_EB 9204#define CLK_EIC_EB 10205#define CLK_INTC_EB 11206#define CLK_ADI_EB 12207#define CLK_AUDIF_EB 13208#define CLK_AUD_EB 14209#define CLK_VBC_EB 15210#define CLK_PIN_EB 16211#define CLK_AP_WDG_EB 17212#define CLK_MM_EB 18213#define CLK_AON_APB_CKG_EB 19214#define CLK_CA53_TS0_EB 20215#define CLK_CA53_TS1_EB 21216#define CLK_CS53_DAP_EB 22217#define CLK_PMU_EB 23218#define CLK_THM_EB 24219#define CLK_AUX0_EB 25220#define CLK_AUX1_EB 26221#define CLK_AUX2_EB 27222#define CLK_PROBE_EB 28223#define CLK_EMC_REF_EB 29224#define CLK_CA53_WDG_EB 30225#define CLK_AP_TMR1_EB 31226#define CLK_AP_TMR2_EB 32227#define CLK_DISP_EMC_EB 33228#define CLK_ZIP_EMC_EB 34229#define CLK_GSP_EMC_EB 35230#define CLK_MM_VSP_EB 36231#define CLK_MDAR_EB 37232#define CLK_RTC4M0_CAL_EB 38233#define CLK_RTC4M1_CAL_EB 39234#define CLK_DJTAG_EB 40235#define CLK_MBOX_EB 41236#define CLK_AON_DMA_EB 42237#define CLK_AON_APB_DEF_EB 43238#define CLK_CA5_TS0_EB 44239#define CLK_DBG_EB 45240#define CLK_DBG_EMC_EB 46241#define CLK_CROSS_TRIG_EB 47242#define CLK_SERDES_DPHY_EB 48243#define CLK_ARCH_RTC_EB 49244#define CLK_KPD_RTC_EB 50245#define CLK_AON_SYST_RTC_EB 51246#define CLK_AP_SYST_RTC_EB 52247#define CLK_AON_TMR_RTC_EB 53248#define CLK_AP_TMR0_RTC_EB 54249#define CLK_EIC_RTC_EB 55250#define CLK_EIC_RTCDV5_EB 56251#define CLK_AP_WDG_RTC_EB 57252#define CLK_CA53_WDG_RTC_EB 58253#define CLK_THM_RTC_EB 59254#define CLK_ATHMA_RTC_EB 60255#define CLK_GTHMA_RTC_EB 61256#define CLK_ATHMA_RTC_A_EB 62257#define CLK_GTHMA_RTC_A_EB 63258#define CLK_AP_TMR1_RTC_EB 64259#define CLK_AP_TMR2_RTC_EB 65260#define CLK_DXCO_LC_RTC_EB 66261#define CLK_BB_CAL_RTC_EB 67262#define CLK_GNU_EB 68263#define CLK_DISP_EB 69264#define CLK_MM_EMC_EB 70265#define CLK_POWER_CPU_EB 71266#define CLK_HW_I2C_EB 72267#define CLK_MM_VSP_EMC_EB 73268#define CLK_VSP_EB 74269#define CLK_CSSYS_EB 75270#define CLK_DMC_EB 76271#define CLK_ROSC_EB 77272#define CLK_S_D_CFG_EB 78273#define CLK_S_D_REF_EB 79274#define CLK_B_DMA_EB 80275#define CLK_ANLG_EB 81276#define CLK_ANLG_APB_EB 82277#define CLK_BSMTMR_EB 83278#define CLK_AP_AXI_EB 84279#define CLK_AP_INTC0_EB 85280#define CLK_AP_INTC1_EB 86281#define CLK_AP_INTC2_EB 87282#define CLK_AP_INTC3_EB 88283#define CLK_AP_INTC4_EB 89284#define CLK_AP_INTC5_EB 90285#define CLK_SCC_EB 91286#define CLK_DPHY_CFG_EB 92287#define CLK_DPHY_REF_EB 93288#define CLK_CPHY_CFG_EB 94289#define CLK_OTG_REF_EB 95290#define CLK_SERDES_EB 96291#define CLK_AON_AP_EMC_EB 97292#define CLK_AON_APB_GATE_NUM (CLK_AON_AP_EMC_EB + 1)293 294#define CLK_MAHB_CKG_EB 0295#define CLK_MDCAM_EB 1296#define CLK_MISP_EB 2297#define CLK_MAHBCSI_EB 3298#define CLK_MCSI_S_EB 4299#define CLK_MCSI_T_EB 5300#define CLK_DCAM_AXI_EB 6301#define CLK_ISP_AXI_EB 7302#define CLK_MCSI_EB 8303#define CLK_MCSI_S_CKG_EB 9304#define CLK_MCSI_T_CKG_EB 10305#define CLK_SENSOR0_EB 11306#define CLK_SENSOR1_EB 12307#define CLK_SENSOR2_EB 13308#define CLK_MCPHY_CFG_EB 14309#define CLK_MM_GATE_NUM (CLK_MCPHY_CFG_EB + 1)310 311#define CLK_MIPI_CSI 0312#define CLK_MIPI_CSI_S 1313#define CLK_MIPI_CSI_M 2314#define CLK_MM_CLK_NUM (CLK_MIPI_CSI_M + 1)315 316#define CLK_SIM0_EB 0317#define CLK_IIS0_EB 1318#define CLK_IIS1_EB 2319#define CLK_IIS2_EB 3320#define CLK_SPI0_EB 4321#define CLK_SPI1_EB 5322#define CLK_SPI2_EB 6323#define CLK_I2C0_EB 7324#define CLK_I2C1_EB 8325#define CLK_I2C2_EB 9326#define CLK_I2C3_EB 10327#define CLK_I2C4_EB 11328#define CLK_UART0_EB 12329#define CLK_UART1_EB 13330#define CLK_UART2_EB 14331#define CLK_UART3_EB 15332#define CLK_UART4_EB 16333#define CLK_SIM0_32K_EB 17334#define CLK_SPI3_EB 18335#define CLK_I2C5_EB 19336#define CLK_I2C6_EB 20337#define CLK_AP_APB_GATE_NUM (CLK_I2C6_EB + 1)338 339#endif /* _DT_BINDINGS_CLK_SC9863A_H_ */340