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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Unisoc UMS512 SoC DTS file4 *5 * Copyright (C) 2022, Unisoc Inc.6 */7 8#ifndef _DT_BINDINGS_CLK_UMS512_H_9#define _DT_BINDINGS_CLK_UMS512_H_10 11#define CLK_26M_AUD 012#define CLK_13M 113#define CLK_6M5 214#define CLK_4M3 315#define CLK_2M 416#define CLK_1M 517#define CLK_250K 618#define CLK_RCO_25M 719#define CLK_RCO_4M 820#define CLK_RCO_2M 921#define CLK_ISPPLL_GATE 1022#define CLK_DPLL0_GATE 1123#define CLK_DPLL1_GATE 1224#define CLK_LPLL_GATE 1325#define CLK_TWPLL_GATE 1426#define CLK_GPLL_GATE 1527#define CLK_RPLL_GATE 1628#define CLK_CPPLL_GATE 1729#define CLK_MPLL0_GATE 1830#define CLK_MPLL1_GATE 1931#define CLK_MPLL2_GATE 2032#define CLK_PMU_GATE_NUM (CLK_MPLL2_GATE + 1)33 34#define CLK_DPLL0 035#define CLK_DPLL0_58M31 136#define CLK_ANLG_PHY_G0_NUM (CLK_DPLL0_58M31 + 1)37 38#define CLK_MPLL1 039#define CLK_MPLL1_63M38 140#define CLK_ANLG_PHY_G2_NUM (CLK_MPLL1_63M38 + 1)41 42#define CLK_RPLL 043#define CLK_AUDIO_GATE 144#define CLK_MPLL0 245#define CLK_MPLL0_56M88 346#define CLK_MPLL2 447#define CLK_MPLL2_47M13 548#define CLK_ANLG_PHY_G3_NUM (CLK_MPLL2_47M13 + 1)49 50#define CLK_TWPLL 051#define CLK_TWPLL_768M 152#define CLK_TWPLL_384M 253#define CLK_TWPLL_192M 354#define CLK_TWPLL_96M 455#define CLK_TWPLL_48M 556#define CLK_TWPLL_24M 657#define CLK_TWPLL_12M 758#define CLK_TWPLL_512M 859#define CLK_TWPLL_256M 960#define CLK_TWPLL_128M 1061#define CLK_TWPLL_64M 1162#define CLK_TWPLL_307M2 1263#define CLK_TWPLL_219M4 1364#define CLK_TWPLL_170M6 1465#define CLK_TWPLL_153M6 1566#define CLK_TWPLL_76M8 1667#define CLK_TWPLL_51M2 1768#define CLK_TWPLL_38M4 1869#define CLK_TWPLL_19M2 1970#define CLK_TWPLL_12M29 2071#define CLK_LPLL 2172#define CLK_LPLL_614M4 2273#define CLK_LPLL_409M6 2374#define CLK_LPLL_245M76 2475#define CLK_LPLL_30M72 2576#define CLK_ISPPLL 2677#define CLK_ISPPLL_468M 2778#define CLK_ISPPLL_78M 2879#define CLK_GPLL 2980#define CLK_GPLL_40M 3081#define CLK_CPPLL 3182#define CLK_CPPLL_39M32 3283#define CLK_ANLG_PHY_GC_NUM (CLK_CPPLL_39M32 + 1)84 85#define CLK_AP_APB 086#define CLK_IPI 187#define CLK_AP_UART0 288#define CLK_AP_UART1 389#define CLK_AP_UART2 490#define CLK_AP_I2C0 591#define CLK_AP_I2C1 692#define CLK_AP_I2C2 793#define CLK_AP_I2C3 894#define CLK_AP_I2C4 995#define CLK_AP_SPI0 1096#define CLK_AP_SPI1 1197#define CLK_AP_SPI2 1298#define CLK_AP_SPI3 1399#define CLK_AP_IIS0 14100#define CLK_AP_IIS1 15101#define CLK_AP_IIS2 16102#define CLK_AP_SIM 17103#define CLK_AP_CE 18104#define CLK_SDIO0_2X 19105#define CLK_SDIO1_2X 20106#define CLK_EMMC_2X 21107#define CLK_VSP 22108#define CLK_DISPC0 23109#define CLK_DISPC0_DPI 24110#define CLK_DSI_APB 25111#define CLK_DSI_RXESC 26112#define CLK_DSI_LANEBYTE 27113#define CLK_VDSP 28114#define CLK_VDSP_M 29115#define CLK_AP_CLK_NUM (CLK_VDSP_M + 1)116 117#define CLK_DSI_EB 0118#define CLK_DISPC_EB 1119#define CLK_VSP_EB 2120#define CLK_VDMA_EB 3121#define CLK_DMA_PUB_EB 4122#define CLK_DMA_SEC_EB 5123#define CLK_IPI_EB 6124#define CLK_AHB_CKG_EB 7125#define CLK_BM_CLK_EB 8126#define CLK_AP_AHB_GATE_NUM (CLK_BM_CLK_EB + 1)127 128#define CLK_AON_APB 0129#define CLK_ADI 1130#define CLK_AUX0 2131#define CLK_AUX1 3132#define CLK_AUX2 4133#define CLK_PROBE 5134#define CLK_PWM0 6135#define CLK_PWM1 7136#define CLK_PWM2 8137#define CLK_PWM3 9138#define CLK_EFUSE 10139#define CLK_UART0 11140#define CLK_UART1 12141#define CLK_THM0 13142#define CLK_THM1 14143#define CLK_THM2 15144#define CLK_THM3 16145#define CLK_AON_I2C 17146#define CLK_AON_IIS 18147#define CLK_SCC 19148#define CLK_APCPU_DAP 20149#define CLK_APCPU_DAP_MTCK 21150#define CLK_APCPU_TS 22151#define CLK_DEBUG_TS 23152#define CLK_DSI_TEST_S 24153#define CLK_DJTAG_TCK 25154#define CLK_DJTAG_TCK_HW 26155#define CLK_AON_TMR 27156#define CLK_AON_PMU 28157#define CLK_DEBOUNCE 29158#define CLK_APCPU_PMU 30159#define CLK_TOP_DVFS 31160#define CLK_OTG_UTMI 32161#define CLK_OTG_REF 33162#define CLK_CSSYS 34163#define CLK_CSSYS_PUB 35164#define CLK_CSSYS_APB 36165#define CLK_AP_AXI 37166#define CLK_AP_MM 38167#define CLK_SDIO2_2X 39168#define CLK_ANALOG_IO_APB 40169#define CLK_DMC_REF_CLK 41170#define CLK_EMC 42171#define CLK_USB 43172#define CLK_26M_PMU 44173#define CLK_AON_APB_NUM (CLK_26M_PMU + 1)174 175#define CLK_MM_AHB 0176#define CLK_MM_MTX 1177#define CLK_SENSOR0 2178#define CLK_SENSOR1 3179#define CLK_SENSOR2 4180#define CLK_CPP 5181#define CLK_JPG 6182#define CLK_FD 7183#define CLK_DCAM_IF 8184#define CLK_DCAM_AXI 9185#define CLK_ISP 10186#define CLK_MIPI_CSI0 11187#define CLK_MIPI_CSI1 12188#define CLK_MIPI_CSI2 13189#define CLK_MM_CLK_NUM (CLK_MIPI_CSI2 + 1)190 191#define CLK_RC100M_CAL_EB 0192#define CLK_DJTAG_TCK_EB 1193#define CLK_DJTAG_EB 2194#define CLK_AUX0_EB 3195#define CLK_AUX1_EB 4196#define CLK_AUX2_EB 5197#define CLK_PROBE_EB 6198#define CLK_MM_EB 7199#define CLK_GPU_EB 8200#define CLK_MSPI_EB 9201#define CLK_APCPU_DAP_EB 10202#define CLK_AON_CSSYS_EB 11203#define CLK_CSSYS_APB_EB 12204#define CLK_CSSYS_PUB_EB 13205#define CLK_SDPHY_CFG_EB 14206#define CLK_SDPHY_REF_EB 15207#define CLK_EFUSE_EB 16208#define CLK_GPIO_EB 17209#define CLK_MBOX_EB 18210#define CLK_KPD_EB 19211#define CLK_AON_SYST_EB 20212#define CLK_AP_SYST_EB 21213#define CLK_AON_TMR_EB 22214#define CLK_OTG_UTMI_EB 23215#define CLK_OTG_PHY_EB 24216#define CLK_SPLK_EB 25217#define CLK_PIN_EB 26218#define CLK_ANA_EB 27219#define CLK_APCPU_TS0_EB 28220#define CLK_APB_BUSMON_EB 29221#define CLK_AON_IIS_EB 30222#define CLK_SCC_EB 31223#define CLK_THM0_EB 32224#define CLK_THM1_EB 33225#define CLK_THM2_EB 34226#define CLK_ASIM_TOP_EB 35227#define CLK_I2C_EB 36228#define CLK_PMU_EB 37229#define CLK_ADI_EB 38230#define CLK_EIC_EB 39231#define CLK_AP_INTC0_EB 40232#define CLK_AP_INTC1_EB 41233#define CLK_AP_INTC2_EB 42234#define CLK_AP_INTC3_EB 43235#define CLK_AP_INTC4_EB 44236#define CLK_AP_INTC5_EB 45237#define CLK_AUDCP_INTC_EB 46238#define CLK_AP_TMR0_EB 47239#define CLK_AP_TMR1_EB 48240#define CLK_AP_TMR2_EB 49241#define CLK_PWM0_EB 50242#define CLK_PWM1_EB 51243#define CLK_PWM2_EB 52244#define CLK_PWM3_EB 53245#define CLK_AP_WDG_EB 54246#define CLK_APCPU_WDG_EB 55247#define CLK_SERDES_EB 56248#define CLK_ARCH_RTC_EB 57249#define CLK_KPD_RTC_EB 58250#define CLK_AON_SYST_RTC_EB 59251#define CLK_AP_SYST_RTC_EB 60252#define CLK_AON_TMR_RTC_EB 61253#define CLK_EIC_RTC_EB 62254#define CLK_EIC_RTCDV5_EB 63255#define CLK_AP_WDG_RTC_EB 64256#define CLK_AC_WDG_RTC_EB 65257#define CLK_AP_TMR0_RTC_EB 66258#define CLK_AP_TMR1_RTC_EB 67259#define CLK_AP_TMR2_RTC_EB 68260#define CLK_DCXO_LC_RTC_EB 69261#define CLK_BB_CAL_RTC_EB 70262#define CLK_AP_EMMC_RTC_EB 71263#define CLK_AP_SDIO0_RTC_EB 72264#define CLK_AP_SDIO1_RTC_EB 73265#define CLK_AP_SDIO2_RTC_EB 74266#define CLK_DSI_CSI_TEST_EB 75267#define CLK_DJTAG_TCK_EN 76268#define CLK_DPHY_REF_EB 77269#define CLK_DMC_REF_EB 78270#define CLK_OTG_REF_EB 79271#define CLK_TSEN_EB 80272#define CLK_TMR_EB 81273#define CLK_RC100M_REF_EB 82274#define CLK_RC100M_FDK_EB 83275#define CLK_DEBOUNCE_EB 84276#define CLK_DET_32K_EB 85277#define CLK_TOP_CSSYS_EB 86278#define CLK_AP_AXI_EN 87279#define CLK_SDIO0_2X_EN 88280#define CLK_SDIO0_1X_EN 89281#define CLK_SDIO1_2X_EN 90282#define CLK_SDIO1_1X_EN 91283#define CLK_SDIO2_2X_EN 92284#define CLK_SDIO2_1X_EN 93285#define CLK_EMMC_2X_EN 94286#define CLK_EMMC_1X_EN 95287#define CLK_PLL_TEST_EN 96288#define CLK_CPHY_CFG_EN 97289#define CLK_DEBUG_TS_EN 98290#define CLK_ACCESS_AUD_EN 99291#define CLK_AON_APB_GATE_NUM (CLK_ACCESS_AUD_EN + 1)292 293#define CLK_MM_CPP_EB 0294#define CLK_MM_JPG_EB 1295#define CLK_MM_DCAM_EB 2296#define CLK_MM_ISP_EB 3297#define CLK_MM_CSI2_EB 4298#define CLK_MM_CSI1_EB 5299#define CLK_MM_CSI0_EB 6300#define CLK_MM_CKG_EB 7301#define CLK_ISP_AHB_EB 8302#define CLK_MM_DVFS_EB 9303#define CLK_MM_FD_EB 10304#define CLK_MM_SENSOR2_EB 11305#define CLK_MM_SENSOR1_EB 12306#define CLK_MM_SENSOR0_EB 13307#define CLK_MM_MIPI_CSI2_EB 14308#define CLK_MM_MIPI_CSI1_EB 15309#define CLK_MM_MIPI_CSI0_EB 16310#define CLK_DCAM_AXI_EB 17311#define CLK_ISP_AXI_EB 18312#define CLK_MM_CPHY_EB 19313#define CLK_MM_GATE_CLK_NUM (CLK_MM_CPHY_EB + 1)314 315#define CLK_SIM0_EB 0316#define CLK_IIS0_EB 1317#define CLK_IIS1_EB 2318#define CLK_IIS2_EB 3319#define CLK_APB_REG_EB 4320#define CLK_SPI0_EB 5321#define CLK_SPI1_EB 6322#define CLK_SPI2_EB 7323#define CLK_SPI3_EB 8324#define CLK_I2C0_EB 9325#define CLK_I2C1_EB 10326#define CLK_I2C2_EB 11327#define CLK_I2C3_EB 12328#define CLK_I2C4_EB 13329#define CLK_UART0_EB 14330#define CLK_UART1_EB 15331#define CLK_UART2_EB 16332#define CLK_SIM0_32K_EB 17333#define CLK_SPI0_LFIN_EB 18334#define CLK_SPI1_LFIN_EB 19335#define CLK_SPI2_LFIN_EB 20336#define CLK_SPI3_LFIN_EB 21337#define CLK_SDIO0_EB 22338#define CLK_SDIO1_EB 23339#define CLK_SDIO2_EB 24340#define CLK_EMMC_EB 25341#define CLK_SDIO0_32K_EB 26342#define CLK_SDIO1_32K_EB 27343#define CLK_SDIO2_32K_EB 28344#define CLK_EMMC_32K_EB 29345#define CLK_AP_APB_GATE_NUM (CLK_EMMC_32K_EB + 1)346 347#define CLK_GPU_CORE_EB 0348#define CLK_GPU_CORE 1349#define CLK_GPU_MEM_EB 2350#define CLK_GPU_MEM 3351#define CLK_GPU_SYS_EB 4352#define CLK_GPU_SYS 5353#define CLK_GPU_CLK_NUM (CLK_GPU_SYS + 1)354 355#define CLK_AUDCP_IIS0_EB 0356#define CLK_AUDCP_IIS1_EB 1357#define CLK_AUDCP_IIS2_EB 2358#define CLK_AUDCP_UART_EB 3359#define CLK_AUDCP_DMA_CP_EB 4360#define CLK_AUDCP_DMA_AP_EB 5361#define CLK_AUDCP_SRC48K_EB 6362#define CLK_AUDCP_MCDT_EB 7363#define CLK_AUDCP_VBCIFD_EB 8364#define CLK_AUDCP_VBC_EB 9365#define CLK_AUDCP_SPLK_EB 10366#define CLK_AUDCP_ICU_EB 11367#define CLK_AUDCP_DMA_AP_ASHB_EB 12368#define CLK_AUDCP_DMA_CP_ASHB_EB 13369#define CLK_AUDCP_AUD_EB 14370#define CLK_AUDCP_VBC_24M_EB 15371#define CLK_AUDCP_TMR_26M_EB 16372#define CLK_AUDCP_DVFS_ASHB_EB 17373#define CLK_AUDCP_AHB_GATE_NUM (CLK_AUDCP_DVFS_ASHB_EB + 1)374 375#define CLK_AUDCP_WDG_EB 0376#define CLK_AUDCP_RTC_WDG_EB 1377#define CLK_AUDCP_TMR0_EB 2378#define CLK_AUDCP_TMR1_EB 3379#define CLK_AUDCP_APB_GATE_NUM (CLK_AUDCP_TMR1_EB + 1)380 381#define CLK_ACORE0 0382#define CLK_ACORE1 1383#define CLK_ACORE2 2384#define CLK_ACORE3 3385#define CLK_ACORE4 4386#define CLK_ACORE5 5387#define CLK_PCORE0 6388#define CLK_PCORE1 7389#define CLK_SCU 8390#define CLK_ACE 9391#define CLK_PERIPH 10392#define CLK_GIC 11393#define CLK_ATB 12394#define CLK_DEBUG_APB 13395#define CLK_APCPU_SEC_NUM (CLK_DEBUG_APB + 1)396 397#endif /* _DT_BINDINGS_CLK_UMS512_H_ */398