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1/* SPDX-License-Identifier: GPL-2.0 OR MIT */2/*3 * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>4 * Copyright 2022 StarFive Technology Co., Ltd.5 */6 7#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__8#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__9 10/* PLL clocks */11#define JH7110_PLLCLK_PLL0_OUT 012#define JH7110_PLLCLK_PLL1_OUT 113#define JH7110_PLLCLK_PLL2_OUT 214#define JH7110_PLLCLK_END 315 16/* SYSCRG clocks */17#define JH7110_SYSCLK_CPU_ROOT 018#define JH7110_SYSCLK_CPU_CORE 119#define JH7110_SYSCLK_CPU_BUS 220#define JH7110_SYSCLK_GPU_ROOT 321#define JH7110_SYSCLK_PERH_ROOT 422#define JH7110_SYSCLK_BUS_ROOT 523#define JH7110_SYSCLK_NOCSTG_BUS 624#define JH7110_SYSCLK_AXI_CFG0 725#define JH7110_SYSCLK_STG_AXIAHB 826#define JH7110_SYSCLK_AHB0 927#define JH7110_SYSCLK_AHB1 1028#define JH7110_SYSCLK_APB_BUS 1129#define JH7110_SYSCLK_APB0 1230#define JH7110_SYSCLK_PLL0_DIV2 1331#define JH7110_SYSCLK_PLL1_DIV2 1432#define JH7110_SYSCLK_PLL2_DIV2 1533#define JH7110_SYSCLK_AUDIO_ROOT 1634#define JH7110_SYSCLK_MCLK_INNER 1735#define JH7110_SYSCLK_MCLK 1836#define JH7110_SYSCLK_MCLK_OUT 1937#define JH7110_SYSCLK_ISP_2X 2038#define JH7110_SYSCLK_ISP_AXI 2139#define JH7110_SYSCLK_GCLK0 2240#define JH7110_SYSCLK_GCLK1 2341#define JH7110_SYSCLK_GCLK2 2442#define JH7110_SYSCLK_CORE 2543#define JH7110_SYSCLK_CORE1 2644#define JH7110_SYSCLK_CORE2 2745#define JH7110_SYSCLK_CORE3 2846#define JH7110_SYSCLK_CORE4 2947#define JH7110_SYSCLK_DEBUG 3048#define JH7110_SYSCLK_RTC_TOGGLE 3149#define JH7110_SYSCLK_TRACE0 3250#define JH7110_SYSCLK_TRACE1 3351#define JH7110_SYSCLK_TRACE2 3452#define JH7110_SYSCLK_TRACE3 3553#define JH7110_SYSCLK_TRACE4 3654#define JH7110_SYSCLK_TRACE_COM 3755#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 3856#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 3957#define JH7110_SYSCLK_OSC_DIV2 4058#define JH7110_SYSCLK_PLL1_DIV4 4159#define JH7110_SYSCLK_PLL1_DIV8 4260#define JH7110_SYSCLK_DDR_BUS 4361#define JH7110_SYSCLK_DDR_AXI 4462#define JH7110_SYSCLK_GPU_CORE 4563#define JH7110_SYSCLK_GPU_CORE_CLK 4664#define JH7110_SYSCLK_GPU_SYS_CLK 4765#define JH7110_SYSCLK_GPU_APB 4866#define JH7110_SYSCLK_GPU_RTC_TOGGLE 4967#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 5068#define JH7110_SYSCLK_ISP_TOP_CORE 5169#define JH7110_SYSCLK_ISP_TOP_AXI 5270#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 5371#define JH7110_SYSCLK_HIFI4_CORE 5472#define JH7110_SYSCLK_HIFI4_AXI 5573#define JH7110_SYSCLK_AXI_CFG1_MAIN 5674#define JH7110_SYSCLK_AXI_CFG1_AHB 5775#define JH7110_SYSCLK_VOUT_SRC 5876#define JH7110_SYSCLK_VOUT_AXI 5977#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 6078#define JH7110_SYSCLK_VOUT_TOP_AHB 6179#define JH7110_SYSCLK_VOUT_TOP_AXI 6280#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 6381#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 6482#define JH7110_SYSCLK_JPEGC_AXI 6583#define JH7110_SYSCLK_CODAJ12_AXI 6684#define JH7110_SYSCLK_CODAJ12_CORE 6785#define JH7110_SYSCLK_CODAJ12_APB 6886#define JH7110_SYSCLK_VDEC_AXI 6987#define JH7110_SYSCLK_WAVE511_AXI 7088#define JH7110_SYSCLK_WAVE511_BPU 7189#define JH7110_SYSCLK_WAVE511_VCE 7290#define JH7110_SYSCLK_WAVE511_APB 7391#define JH7110_SYSCLK_VDEC_JPG 7492#define JH7110_SYSCLK_VDEC_MAIN 7593#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 7694#define JH7110_SYSCLK_VENC_AXI 7795#define JH7110_SYSCLK_WAVE420L_AXI 7896#define JH7110_SYSCLK_WAVE420L_BPU 7997#define JH7110_SYSCLK_WAVE420L_VCE 8098#define JH7110_SYSCLK_WAVE420L_APB 8199#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82100#define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83101#define JH7110_SYSCLK_AXI_CFG0_MAIN 84102#define JH7110_SYSCLK_AXI_CFG0_HIFI4 85103#define JH7110_SYSCLK_AXIMEM2_AXI 86104#define JH7110_SYSCLK_QSPI_AHB 87105#define JH7110_SYSCLK_QSPI_APB 88106#define JH7110_SYSCLK_QSPI_REF_SRC 89107#define JH7110_SYSCLK_QSPI_REF 90108#define JH7110_SYSCLK_SDIO0_AHB 91109#define JH7110_SYSCLK_SDIO1_AHB 92110#define JH7110_SYSCLK_SDIO0_SDCARD 93111#define JH7110_SYSCLK_SDIO1_SDCARD 94112#define JH7110_SYSCLK_USB_125M 95113#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96114#define JH7110_SYSCLK_GMAC1_AHB 97115#define JH7110_SYSCLK_GMAC1_AXI 98116#define JH7110_SYSCLK_GMAC_SRC 99117#define JH7110_SYSCLK_GMAC1_GTXCLK 100118#define JH7110_SYSCLK_GMAC1_RMII_RTX 101119#define JH7110_SYSCLK_GMAC1_PTP 102120#define JH7110_SYSCLK_GMAC1_RX 103121#define JH7110_SYSCLK_GMAC1_RX_INV 104122#define JH7110_SYSCLK_GMAC1_TX 105123#define JH7110_SYSCLK_GMAC1_TX_INV 106124#define JH7110_SYSCLK_GMAC1_GTXC 107125#define JH7110_SYSCLK_GMAC0_GTXCLK 108126#define JH7110_SYSCLK_GMAC0_PTP 109127#define JH7110_SYSCLK_GMAC_PHY 110128#define JH7110_SYSCLK_GMAC0_GTXC 111129#define JH7110_SYSCLK_IOMUX_APB 112130#define JH7110_SYSCLK_MAILBOX_APB 113131#define JH7110_SYSCLK_INT_CTRL_APB 114132#define JH7110_SYSCLK_CAN0_APB 115133#define JH7110_SYSCLK_CAN0_TIMER 116134#define JH7110_SYSCLK_CAN0_CAN 117135#define JH7110_SYSCLK_CAN1_APB 118136#define JH7110_SYSCLK_CAN1_TIMER 119137#define JH7110_SYSCLK_CAN1_CAN 120138#define JH7110_SYSCLK_PWM_APB 121139#define JH7110_SYSCLK_WDT_APB 122140#define JH7110_SYSCLK_WDT_CORE 123141#define JH7110_SYSCLK_TIMER_APB 124142#define JH7110_SYSCLK_TIMER0 125143#define JH7110_SYSCLK_TIMER1 126144#define JH7110_SYSCLK_TIMER2 127145#define JH7110_SYSCLK_TIMER3 128146#define JH7110_SYSCLK_TEMP_APB 129147#define JH7110_SYSCLK_TEMP_CORE 130148#define JH7110_SYSCLK_SPI0_APB 131149#define JH7110_SYSCLK_SPI1_APB 132150#define JH7110_SYSCLK_SPI2_APB 133151#define JH7110_SYSCLK_SPI3_APB 134152#define JH7110_SYSCLK_SPI4_APB 135153#define JH7110_SYSCLK_SPI5_APB 136154#define JH7110_SYSCLK_SPI6_APB 137155#define JH7110_SYSCLK_I2C0_APB 138156#define JH7110_SYSCLK_I2C1_APB 139157#define JH7110_SYSCLK_I2C2_APB 140158#define JH7110_SYSCLK_I2C3_APB 141159#define JH7110_SYSCLK_I2C4_APB 142160#define JH7110_SYSCLK_I2C5_APB 143161#define JH7110_SYSCLK_I2C6_APB 144162#define JH7110_SYSCLK_UART0_APB 145163#define JH7110_SYSCLK_UART0_CORE 146164#define JH7110_SYSCLK_UART1_APB 147165#define JH7110_SYSCLK_UART1_CORE 148166#define JH7110_SYSCLK_UART2_APB 149167#define JH7110_SYSCLK_UART2_CORE 150168#define JH7110_SYSCLK_UART3_APB 151169#define JH7110_SYSCLK_UART3_CORE 152170#define JH7110_SYSCLK_UART4_APB 153171#define JH7110_SYSCLK_UART4_CORE 154172#define JH7110_SYSCLK_UART5_APB 155173#define JH7110_SYSCLK_UART5_CORE 156174#define JH7110_SYSCLK_PWMDAC_APB 157175#define JH7110_SYSCLK_PWMDAC_CORE 158176#define JH7110_SYSCLK_SPDIF_APB 159177#define JH7110_SYSCLK_SPDIF_CORE 160178#define JH7110_SYSCLK_I2STX0_APB 161179#define JH7110_SYSCLK_I2STX0_BCLK_MST 162180#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163181#define JH7110_SYSCLK_I2STX0_LRCK_MST 164182#define JH7110_SYSCLK_I2STX0_BCLK 165183#define JH7110_SYSCLK_I2STX0_BCLK_INV 166184#define JH7110_SYSCLK_I2STX0_LRCK 167185#define JH7110_SYSCLK_I2STX1_APB 168186#define JH7110_SYSCLK_I2STX1_BCLK_MST 169187#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170188#define JH7110_SYSCLK_I2STX1_LRCK_MST 171189#define JH7110_SYSCLK_I2STX1_BCLK 172190#define JH7110_SYSCLK_I2STX1_BCLK_INV 173191#define JH7110_SYSCLK_I2STX1_LRCK 174192#define JH7110_SYSCLK_I2SRX_APB 175193#define JH7110_SYSCLK_I2SRX_BCLK_MST 176194#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177195#define JH7110_SYSCLK_I2SRX_LRCK_MST 178196#define JH7110_SYSCLK_I2SRX_BCLK 179197#define JH7110_SYSCLK_I2SRX_BCLK_INV 180198#define JH7110_SYSCLK_I2SRX_LRCK 181199#define JH7110_SYSCLK_PDM_DMIC 182200#define JH7110_SYSCLK_PDM_APB 183201#define JH7110_SYSCLK_TDM_AHB 184202#define JH7110_SYSCLK_TDM_APB 185203#define JH7110_SYSCLK_TDM_INTERNAL 186204#define JH7110_SYSCLK_TDM_TDM 187205#define JH7110_SYSCLK_TDM_TDM_INV 188206#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189207 208#define JH7110_SYSCLK_END 190209 210/* AONCRG clocks */211#define JH7110_AONCLK_OSC_DIV4 0212#define JH7110_AONCLK_APB_FUNC 1213#define JH7110_AONCLK_GMAC0_AHB 2214#define JH7110_AONCLK_GMAC0_AXI 3215#define JH7110_AONCLK_GMAC0_RMII_RTX 4216#define JH7110_AONCLK_GMAC0_TX 5217#define JH7110_AONCLK_GMAC0_TX_INV 6218#define JH7110_AONCLK_GMAC0_RX 7219#define JH7110_AONCLK_GMAC0_RX_INV 8220#define JH7110_AONCLK_OTPC_APB 9221#define JH7110_AONCLK_RTC_APB 10222#define JH7110_AONCLK_RTC_INTERNAL 11223#define JH7110_AONCLK_RTC_32K 12224#define JH7110_AONCLK_RTC_CAL 13225 226#define JH7110_AONCLK_END 14227 228/* STGCRG clocks */229#define JH7110_STGCLK_HIFI4_CLK_CORE 0230#define JH7110_STGCLK_USB0_APB 1231#define JH7110_STGCLK_USB0_UTMI_APB 2232#define JH7110_STGCLK_USB0_AXI 3233#define JH7110_STGCLK_USB0_LPM 4234#define JH7110_STGCLK_USB0_STB 5235#define JH7110_STGCLK_USB0_APP_125 6236#define JH7110_STGCLK_USB0_REFCLK 7237#define JH7110_STGCLK_PCIE0_AXI_MST0 8238#define JH7110_STGCLK_PCIE0_APB 9239#define JH7110_STGCLK_PCIE0_TL 10240#define JH7110_STGCLK_PCIE1_AXI_MST0 11241#define JH7110_STGCLK_PCIE1_APB 12242#define JH7110_STGCLK_PCIE1_TL 13243#define JH7110_STGCLK_PCIE_SLV_MAIN 14244#define JH7110_STGCLK_SEC_AHB 15245#define JH7110_STGCLK_SEC_MISC_AHB 16246#define JH7110_STGCLK_GRP0_MAIN 17247#define JH7110_STGCLK_GRP0_BUS 18248#define JH7110_STGCLK_GRP0_STG 19249#define JH7110_STGCLK_GRP1_MAIN 20250#define JH7110_STGCLK_GRP1_BUS 21251#define JH7110_STGCLK_GRP1_STG 22252#define JH7110_STGCLK_GRP1_HIFI 23253#define JH7110_STGCLK_E2_RTC 24254#define JH7110_STGCLK_E2_CORE 25255#define JH7110_STGCLK_E2_DBG 26256#define JH7110_STGCLK_DMA1P_AXI 27257#define JH7110_STGCLK_DMA1P_AHB 28258 259#define JH7110_STGCLK_END 29260 261/* ISPCRG clocks */262#define JH7110_ISPCLK_DOM4_APB_FUNC 0263#define JH7110_ISPCLK_MIPI_RX0_PXL 1264#define JH7110_ISPCLK_DVP_INV 2265#define JH7110_ISPCLK_M31DPHY_CFG_IN 3266#define JH7110_ISPCLK_M31DPHY_REF_IN 4267#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5268#define JH7110_ISPCLK_VIN_APB 6269#define JH7110_ISPCLK_VIN_SYS 7270#define JH7110_ISPCLK_VIN_PIXEL_IF0 8271#define JH7110_ISPCLK_VIN_PIXEL_IF1 9272#define JH7110_ISPCLK_VIN_PIXEL_IF2 10273#define JH7110_ISPCLK_VIN_PIXEL_IF3 11274#define JH7110_ISPCLK_VIN_P_AXI_WR 12275#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13276 277#define JH7110_ISPCLK_END 14278 279/* VOUTCRG clocks */280#define JH7110_VOUTCLK_APB 0281#define JH7110_VOUTCLK_DC8200_PIX 1282#define JH7110_VOUTCLK_DSI_SYS 2283#define JH7110_VOUTCLK_TX_ESC 3284#define JH7110_VOUTCLK_DC8200_AXI 4285#define JH7110_VOUTCLK_DC8200_CORE 5286#define JH7110_VOUTCLK_DC8200_AHB 6287#define JH7110_VOUTCLK_DC8200_PIX0 7288#define JH7110_VOUTCLK_DC8200_PIX1 8289#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9290#define JH7110_VOUTCLK_DSITX_APB 10291#define JH7110_VOUTCLK_DSITX_SYS 11292#define JH7110_VOUTCLK_DSITX_DPI 12293#define JH7110_VOUTCLK_DSITX_TXESC 13294#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14295#define JH7110_VOUTCLK_HDMI_TX_MCLK 15296#define JH7110_VOUTCLK_HDMI_TX_BCLK 16297#define JH7110_VOUTCLK_HDMI_TX_SYS 17298 299#define JH7110_VOUTCLK_END 18300 301#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */302