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1/* SPDX-License-Identifier: GPL-2.0 OR MIT */2/*3 * Copyright (C) 2021 Ahmad Fatoum, Pengutronix4 */5 6#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__7#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__8 9#define JH7100_CLK_CPUNDBUS_ROOT 010#define JH7100_CLK_DLA_ROOT 111#define JH7100_CLK_DSP_ROOT 212#define JH7100_CLK_GMACUSB_ROOT 313#define JH7100_CLK_PERH0_ROOT 414#define JH7100_CLK_PERH1_ROOT 515#define JH7100_CLK_VIN_ROOT 616#define JH7100_CLK_VOUT_ROOT 717#define JH7100_CLK_AUDIO_ROOT 818#define JH7100_CLK_CDECHIFI4_ROOT 919#define JH7100_CLK_CDEC_ROOT 1020#define JH7100_CLK_VOUTBUS_ROOT 1121#define JH7100_CLK_CPUNBUS_ROOT_DIV 1222#define JH7100_CLK_DSP_ROOT_DIV 1323#define JH7100_CLK_PERH0_SRC 1424#define JH7100_CLK_PERH1_SRC 1525#define JH7100_CLK_PLL0_TESTOUT 1626#define JH7100_CLK_PLL1_TESTOUT 1727#define JH7100_CLK_PLL2_TESTOUT 1828#define JH7100_CLK_PLL2_REF 1929#define JH7100_CLK_CPU_CORE 2030#define JH7100_CLK_CPU_AXI 2131#define JH7100_CLK_AHB_BUS 2232#define JH7100_CLK_APB1_BUS 2333#define JH7100_CLK_APB2_BUS 2434#define JH7100_CLK_DOM3AHB_BUS 2535#define JH7100_CLK_DOM7AHB_BUS 2636#define JH7100_CLK_U74_CORE0 2737#define JH7100_CLK_U74_CORE1 2838#define JH7100_CLK_U74_AXI 2939#define JH7100_CLK_U74RTC_TOGGLE 3040#define JH7100_CLK_SGDMA2P_AXI 3141#define JH7100_CLK_DMA2PNOC_AXI 3242#define JH7100_CLK_SGDMA2P_AHB 3343#define JH7100_CLK_DLA_BUS 3444#define JH7100_CLK_DLA_AXI 3545#define JH7100_CLK_DLANOC_AXI 3646#define JH7100_CLK_DLA_APB 3747#define JH7100_CLK_VP6_CORE 3848#define JH7100_CLK_VP6BUS_SRC 3949#define JH7100_CLK_VP6_AXI 4050#define JH7100_CLK_VCDECBUS_SRC 4151#define JH7100_CLK_VDEC_BUS 4252#define JH7100_CLK_VDEC_AXI 4353#define JH7100_CLK_VDECBRG_MAIN 4454#define JH7100_CLK_VDEC_BCLK 4555#define JH7100_CLK_VDEC_CCLK 4656#define JH7100_CLK_VDEC_APB 4757#define JH7100_CLK_JPEG_AXI 4858#define JH7100_CLK_JPEG_CCLK 4959#define JH7100_CLK_JPEG_APB 5060#define JH7100_CLK_GC300_2X 5161#define JH7100_CLK_GC300_AHB 5262#define JH7100_CLK_JPCGC300_AXIBUS 5363#define JH7100_CLK_GC300_AXI 5464#define JH7100_CLK_JPCGC300_MAIN 5565#define JH7100_CLK_VENC_BUS 5666#define JH7100_CLK_VENC_AXI 5767#define JH7100_CLK_VENCBRG_MAIN 5868#define JH7100_CLK_VENC_BCLK 5969#define JH7100_CLK_VENC_CCLK 6070#define JH7100_CLK_VENC_APB 6171#define JH7100_CLK_DDRPLL_DIV2 6272#define JH7100_CLK_DDRPLL_DIV4 6373#define JH7100_CLK_DDRPLL_DIV8 6474#define JH7100_CLK_DDROSC_DIV2 6575#define JH7100_CLK_DDRC0 6676#define JH7100_CLK_DDRC1 6777#define JH7100_CLK_DDRPHY_APB 6878#define JH7100_CLK_NOC_ROB 6979#define JH7100_CLK_NOC_COG 7080#define JH7100_CLK_NNE_AHB 7181#define JH7100_CLK_NNEBUS_SRC1 7282#define JH7100_CLK_NNE_BUS 7383#define JH7100_CLK_NNE_AXI 7484#define JH7100_CLK_NNENOC_AXI 7585#define JH7100_CLK_DLASLV_AXI 7686#define JH7100_CLK_DSPX2C_AXI 7787#define JH7100_CLK_HIFI4_SRC 7888#define JH7100_CLK_HIFI4_COREFREE 7989#define JH7100_CLK_HIFI4_CORE 8090#define JH7100_CLK_HIFI4_BUS 8191#define JH7100_CLK_HIFI4_AXI 8292#define JH7100_CLK_HIFI4NOC_AXI 8393#define JH7100_CLK_SGDMA1P_BUS 8494#define JH7100_CLK_SGDMA1P_AXI 8595#define JH7100_CLK_DMA1P_AXI 8696#define JH7100_CLK_X2C_AXI 8797#define JH7100_CLK_USB_BUS 8898#define JH7100_CLK_USB_AXI 8999#define JH7100_CLK_USBNOC_AXI 90100#define JH7100_CLK_USBPHY_ROOTDIV 91101#define JH7100_CLK_USBPHY_125M 92102#define JH7100_CLK_USBPHY_PLLDIV25M 93103#define JH7100_CLK_USBPHY_25M 94104#define JH7100_CLK_AUDIO_DIV 95105#define JH7100_CLK_AUDIO_SRC 96106#define JH7100_CLK_AUDIO_12288 97107#define JH7100_CLK_VIN_SRC 98108#define JH7100_CLK_ISP0_BUS 99109#define JH7100_CLK_ISP0_AXI 100110#define JH7100_CLK_ISP0NOC_AXI 101111#define JH7100_CLK_ISPSLV_AXI 102112#define JH7100_CLK_ISP1_BUS 103113#define JH7100_CLK_ISP1_AXI 104114#define JH7100_CLK_ISP1NOC_AXI 105115#define JH7100_CLK_VIN_BUS 106116#define JH7100_CLK_VIN_AXI 107117#define JH7100_CLK_VINNOC_AXI 108118#define JH7100_CLK_VOUT_SRC 109119#define JH7100_CLK_DISPBUS_SRC 110120#define JH7100_CLK_DISP_BUS 111121#define JH7100_CLK_DISP_AXI 112122#define JH7100_CLK_DISPNOC_AXI 113123#define JH7100_CLK_SDIO0_AHB 114124#define JH7100_CLK_SDIO0_CCLKINT 115125#define JH7100_CLK_SDIO0_CCLKINT_INV 116126#define JH7100_CLK_SDIO1_AHB 117127#define JH7100_CLK_SDIO1_CCLKINT 118128#define JH7100_CLK_SDIO1_CCLKINT_INV 119129#define JH7100_CLK_GMAC_AHB 120130#define JH7100_CLK_GMAC_ROOT_DIV 121131#define JH7100_CLK_GMAC_PTP_REF 122132#define JH7100_CLK_GMAC_GTX 123133#define JH7100_CLK_GMAC_RMII_TX 124134#define JH7100_CLK_GMAC_RMII_RX 125135#define JH7100_CLK_GMAC_TX 126136#define JH7100_CLK_GMAC_TX_INV 127137#define JH7100_CLK_GMAC_RX_PRE 128138#define JH7100_CLK_GMAC_RX_INV 129139#define JH7100_CLK_GMAC_RMII 130140#define JH7100_CLK_GMAC_TOPHYREF 131141#define JH7100_CLK_SPI2AHB_AHB 132142#define JH7100_CLK_SPI2AHB_CORE 133143#define JH7100_CLK_EZMASTER_AHB 134144#define JH7100_CLK_E24_AHB 135145#define JH7100_CLK_E24RTC_TOGGLE 136146#define JH7100_CLK_QSPI_AHB 137147#define JH7100_CLK_QSPI_APB 138148#define JH7100_CLK_QSPI_REF 139149#define JH7100_CLK_SEC_AHB 140150#define JH7100_CLK_AES 141151#define JH7100_CLK_SHA 142152#define JH7100_CLK_PKA 143153#define JH7100_CLK_TRNG_APB 144154#define JH7100_CLK_OTP_APB 145155#define JH7100_CLK_UART0_APB 146156#define JH7100_CLK_UART0_CORE 147157#define JH7100_CLK_UART1_APB 148158#define JH7100_CLK_UART1_CORE 149159#define JH7100_CLK_SPI0_APB 150160#define JH7100_CLK_SPI0_CORE 151161#define JH7100_CLK_SPI1_APB 152162#define JH7100_CLK_SPI1_CORE 153163#define JH7100_CLK_I2C0_APB 154164#define JH7100_CLK_I2C0_CORE 155165#define JH7100_CLK_I2C1_APB 156166#define JH7100_CLK_I2C1_CORE 157167#define JH7100_CLK_GPIO_APB 158168#define JH7100_CLK_UART2_APB 159169#define JH7100_CLK_UART2_CORE 160170#define JH7100_CLK_UART3_APB 161171#define JH7100_CLK_UART3_CORE 162172#define JH7100_CLK_SPI2_APB 163173#define JH7100_CLK_SPI2_CORE 164174#define JH7100_CLK_SPI3_APB 165175#define JH7100_CLK_SPI3_CORE 166176#define JH7100_CLK_I2C2_APB 167177#define JH7100_CLK_I2C2_CORE 168178#define JH7100_CLK_I2C3_APB 169179#define JH7100_CLK_I2C3_CORE 170180#define JH7100_CLK_WDTIMER_APB 171181#define JH7100_CLK_WDT_CORE 172182#define JH7100_CLK_TIMER0_CORE 173183#define JH7100_CLK_TIMER1_CORE 174184#define JH7100_CLK_TIMER2_CORE 175185#define JH7100_CLK_TIMER3_CORE 176186#define JH7100_CLK_TIMER4_CORE 177187#define JH7100_CLK_TIMER5_CORE 178188#define JH7100_CLK_TIMER6_CORE 179189#define JH7100_CLK_VP6INTC_APB 180190#define JH7100_CLK_PWM_APB 181191#define JH7100_CLK_MSI_APB 182192#define JH7100_CLK_TEMP_APB 183193#define JH7100_CLK_TEMP_SENSE 184194#define JH7100_CLK_SYSERR_APB 185195 196#define JH7100_CLK_PLL0_OUT 186197#define JH7100_CLK_PLL1_OUT 187198#define JH7100_CLK_PLL2_OUT 188199 200#define JH7100_CLK_END 189201 202#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */203