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1/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */2/*3 * Copyright (C) STMicroelectronics 2020 - All Rights Reserved4 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.5 */6 7#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_8#define _DT_BINDINGS_STM32MP13_CLKS_H_9 10/* OSCILLATOR clocks */11#define CK_HSE 012#define CK_CSI 113#define CK_LSI 214#define CK_LSE 315#define CK_HSI 416#define CK_HSE_DIV2 517 18/* PLL */19#define PLL1 620#define PLL2 721#define PLL3 822#define PLL4 923 24/* ODF */25#define PLL1_P 1026#define PLL1_Q 1127#define PLL1_R 1228#define PLL2_P 1329#define PLL2_Q 1430#define PLL2_R 1531#define PLL3_P 1632#define PLL3_Q 1733#define PLL3_R 1834#define PLL4_P 1935#define PLL4_Q 2036#define PLL4_R 2137 38#define PCLK1 2239#define PCLK2 2340#define PCLK3 2441#define PCLK4 2542#define PCLK5 2643#define PCLK6 2744 45/* SYSTEM CLOCK */46#define CK_PER 2847#define CK_MPU 2948#define CK_AXI 3049#define CK_MLAHB 3150 51/* BASE TIMER */52#define CK_TIMG1 3253#define CK_TIMG2 3354#define CK_TIMG3 3455 56/* AUX */57#define RTC 3558 59/* TRACE & DEBUG clocks */60#define CK_DBG 3661#define CK_TRACE 3762 63/* MCO clocks */64#define CK_MCO1 3865#define CK_MCO2 3966 67/* IP clocks */68#define SYSCFG 4069#define VREF 4170#define DTS 4271#define PMBCTRL 4372#define HDP 4473#define IWDG2 4574#define STGENRO 4675#define USART1 4776#define RTCAPB 4877#define TZC 4978#define TZPC 5079#define IWDG1 5180#define BSEC 5281#define DMA1 5382#define DMA2 5483#define DMAMUX1 5584#define DMAMUX2 5685#define GPIOA 5786#define GPIOB 5887#define GPIOC 5988#define GPIOD 6089#define GPIOE 6190#define GPIOF 6291#define GPIOG 6392#define GPIOH 6493#define GPIOI 6594#define CRYP1 6695#define HASH1 6796#define BKPSRAM 6897#define MDMA 6998#define CRC1 7099#define USBH 71100#define DMA3 72101#define TSC 73102#define PKA 74103#define AXIMC 75104#define MCE 76105#define ETH1TX 77106#define ETH2TX 78107#define ETH1RX 79108#define ETH2RX 80109#define ETH1MAC 81110#define ETH2MAC 82111#define ETH1STP 83112#define ETH2STP 84113 114/* IP clocks with parents */115#define SDMMC1_K 85116#define SDMMC2_K 86117#define ADC1_K 87118#define ADC2_K 88119#define FMC_K 89120#define QSPI_K 90121#define RNG1_K 91122#define USBPHY_K 92123#define STGEN_K 93124#define SPDIF_K 94125#define SPI1_K 95126#define SPI2_K 96127#define SPI3_K 97128#define SPI4_K 98129#define SPI5_K 99130#define I2C1_K 100131#define I2C2_K 101132#define I2C3_K 102133#define I2C4_K 103134#define I2C5_K 104135#define TIM2_K 105136#define TIM3_K 106137#define TIM4_K 107138#define TIM5_K 108139#define TIM6_K 109140#define TIM7_K 110141#define TIM12_K 111142#define TIM13_K 112143#define TIM14_K 113144#define TIM1_K 114145#define TIM8_K 115146#define TIM15_K 116147#define TIM16_K 117148#define TIM17_K 118149#define LPTIM1_K 119150#define LPTIM2_K 120151#define LPTIM3_K 121152#define LPTIM4_K 122153#define LPTIM5_K 123154#define USART1_K 124155#define USART2_K 125156#define USART3_K 126157#define UART4_K 127158#define UART5_K 128159#define USART6_K 129160#define UART7_K 130161#define UART8_K 131162#define DFSDM_K 132163#define FDCAN_K 133164#define SAI1_K 134165#define SAI2_K 135166#define ADFSDM_K 136167#define USBO_K 137168#define LTDC_PX 138169#define ETH1CK_K 139170#define ETH1PTP_K 140171#define ETH2CK_K 141172#define ETH2PTP_K 142173#define DCMIPP_K 143174#define SAES_K 144175#define DTS_K 145176 177/* DDR */178#define DDRC1 146179#define DDRC1LP 147180#define DDRC2 148181#define DDRC2LP 149182#define DDRPHYC 150183#define DDRPHYCLP 151184#define DDRCAPB 152185#define DDRCAPBLP 153186#define AXIDCG 154187#define DDRPHYCAPB 155188#define DDRPHYCAPBLP 156189#define DDRPERFM 157190 191#define ADC1 158192#define ADC2 159193#define SAI1 160194#define SAI2 161195 196#define STM32MP1_LAST_CLK 162197 198/* SCMI clock identifiers */199#define CK_SCMI_HSE 0200#define CK_SCMI_HSI 1201#define CK_SCMI_CSI 2202#define CK_SCMI_LSE 3203#define CK_SCMI_LSI 4204#define CK_SCMI_HSE_DIV2 5205#define CK_SCMI_PLL2_Q 6206#define CK_SCMI_PLL2_R 7207#define CK_SCMI_PLL3_P 8208#define CK_SCMI_PLL3_Q 9209#define CK_SCMI_PLL3_R 10210#define CK_SCMI_PLL4_P 11211#define CK_SCMI_PLL4_Q 12212#define CK_SCMI_PLL4_R 13213#define CK_SCMI_MPU 14214#define CK_SCMI_AXI 15215#define CK_SCMI_MLAHB 16216#define CK_SCMI_CKPER 17217#define CK_SCMI_PCLK1 18218#define CK_SCMI_PCLK2 19219#define CK_SCMI_PCLK3 20220#define CK_SCMI_PCLK4 21221#define CK_SCMI_PCLK5 22222#define CK_SCMI_PCLK6 23223#define CK_SCMI_CKTIMG1 24224#define CK_SCMI_CKTIMG2 25225#define CK_SCMI_CKTIMG3 26226#define CK_SCMI_RTC 27227#define CK_SCMI_RTCAPB 28228 229#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */230