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1/*2 * Copyright (C) 2017 Priit Laes <plaes@plaes.org>3 *4 * This file is dual-licensed: you can use it either under the terms5 * of the GPL or the X11 license, at your option. Note that this dual6 * licensing only applies to this file, and not this project as a7 * whole.8 *9 * a) This file is free software; you can redistribute it and/or10 * modify it under the terms of the GNU General Public License as11 * published by the Free Software Foundation; either version 2 of the12 * License, or (at your option) any later version.13 *14 * This file is distributed in the hope that it will be useful,15 * but WITHOUT ANY WARRANTY; without even the implied warranty of16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the17 * GNU General Public License for more details.18 *19 * Or, alternatively,20 *21 * b) Permission is hereby granted, free of charge, to any person22 * obtaining a copy of this software and associated documentation23 * files (the "Software"), to deal in the Software without24 * restriction, including without limitation the rights to use,25 * copy, modify, merge, publish, distribute, sublicense, and/or26 * sell copies of the Software, and to permit persons to whom the27 * Software is furnished to do so, subject to the following28 * conditions:29 *30 * The above copyright notice and this permission notice shall be31 * included in all copies or substantial portions of the Software.32 *33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR39 * OTHER DEALINGS IN THE SOFTWARE.40 */41 42#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_43#define _DT_BINDINGS_CLK_SUN4I_A10_H_44 45#define CLK_HOSC 146#define CLK_PLL_VIDEO0_2X 947#define CLK_PLL_VIDEO1_2X 1848#define CLK_CPU 2049 50/* AHB Gates */51#define CLK_AHB_OTG 2652#define CLK_AHB_EHCI0 2753#define CLK_AHB_OHCI0 2854#define CLK_AHB_EHCI1 2955#define CLK_AHB_OHCI1 3056#define CLK_AHB_SS 3157#define CLK_AHB_DMA 3258#define CLK_AHB_BIST 3359#define CLK_AHB_MMC0 3460#define CLK_AHB_MMC1 3561#define CLK_AHB_MMC2 3662#define CLK_AHB_MMC3 3763#define CLK_AHB_MS 3864#define CLK_AHB_NAND 3965#define CLK_AHB_SDRAM 4066#define CLK_AHB_ACE 4167#define CLK_AHB_EMAC 4268#define CLK_AHB_TS 4369#define CLK_AHB_SPI0 4470#define CLK_AHB_SPI1 4571#define CLK_AHB_SPI2 4672#define CLK_AHB_SPI3 4773#define CLK_AHB_PATA 4874#define CLK_AHB_SATA 4975#define CLK_AHB_GPS 5076#define CLK_AHB_HSTIMER 5177#define CLK_AHB_VE 5278#define CLK_AHB_TVD 5379#define CLK_AHB_TVE0 5480#define CLK_AHB_TVE1 5581#define CLK_AHB_LCD0 5682#define CLK_AHB_LCD1 5783#define CLK_AHB_CSI0 5884#define CLK_AHB_CSI1 5985#define CLK_AHB_HDMI0 6086#define CLK_AHB_HDMI1 6187#define CLK_AHB_DE_BE0 6288#define CLK_AHB_DE_BE1 6389#define CLK_AHB_DE_FE0 6490#define CLK_AHB_DE_FE1 6591#define CLK_AHB_GMAC 6692#define CLK_AHB_MP 6793#define CLK_AHB_GPU 6894 95/* APB0 Gates */96#define CLK_APB0_CODEC 6997#define CLK_APB0_SPDIF 7098#define CLK_APB0_I2S0 7199#define CLK_APB0_AC97 72100#define CLK_APB0_I2S1 73101#define CLK_APB0_PIO 74102#define CLK_APB0_IR0 75103#define CLK_APB0_IR1 76104#define CLK_APB0_I2S2 77105#define CLK_APB0_KEYPAD 78106 107/* APB1 Gates */108#define CLK_APB1_I2C0 79109#define CLK_APB1_I2C1 80110#define CLK_APB1_I2C2 81111#define CLK_APB1_I2C3 82112#define CLK_APB1_CAN 83113#define CLK_APB1_SCR 84114#define CLK_APB1_PS20 85115#define CLK_APB1_PS21 86116#define CLK_APB1_I2C4 87117#define CLK_APB1_UART0 88118#define CLK_APB1_UART1 89119#define CLK_APB1_UART2 90120#define CLK_APB1_UART3 91121#define CLK_APB1_UART4 92122#define CLK_APB1_UART5 93123#define CLK_APB1_UART6 94124#define CLK_APB1_UART7 95125 126/* IP clocks */127#define CLK_NAND 96128#define CLK_MS 97129#define CLK_MMC0 98130#define CLK_MMC0_OUTPUT 99131#define CLK_MMC0_SAMPLE 100132#define CLK_MMC1 101133#define CLK_MMC1_OUTPUT 102134#define CLK_MMC1_SAMPLE 103135#define CLK_MMC2 104136#define CLK_MMC2_OUTPUT 105137#define CLK_MMC2_SAMPLE 106138#define CLK_MMC3 107139#define CLK_MMC3_OUTPUT 108140#define CLK_MMC3_SAMPLE 109141#define CLK_TS 110142#define CLK_SS 111143#define CLK_SPI0 112144#define CLK_SPI1 113145#define CLK_SPI2 114146#define CLK_PATA 115147#define CLK_IR0 116148#define CLK_IR1 117149#define CLK_I2S0 118150#define CLK_AC97 119151#define CLK_SPDIF 120152#define CLK_KEYPAD 121153#define CLK_SATA 122154#define CLK_USB_OHCI0 123155#define CLK_USB_OHCI1 124156#define CLK_USB_PHY 125157#define CLK_GPS 126158#define CLK_SPI3 127159#define CLK_I2S1 128160#define CLK_I2S2 129161 162/* DRAM Gates */163#define CLK_DRAM_VE 130164#define CLK_DRAM_CSI0 131165#define CLK_DRAM_CSI1 132166#define CLK_DRAM_TS 133167#define CLK_DRAM_TVD 134168#define CLK_DRAM_TVE0 135169#define CLK_DRAM_TVE1 136170#define CLK_DRAM_OUT 137171#define CLK_DRAM_DE_FE1 138172#define CLK_DRAM_DE_FE0 139173#define CLK_DRAM_DE_BE0 140174#define CLK_DRAM_DE_BE1 141175#define CLK_DRAM_MP 142176#define CLK_DRAM_ACE 143177 178/* Display Engine Clocks */179#define CLK_DE_BE0 144180#define CLK_DE_BE1 145181#define CLK_DE_FE0 146182#define CLK_DE_FE1 147183#define CLK_DE_MP 148184#define CLK_TCON0_CH0 149185#define CLK_TCON1_CH0 150186#define CLK_CSI_SCLK 151187#define CLK_TVD_SCLK2 152188#define CLK_TVD 153189#define CLK_TCON0_CH1_SCLK2 154190#define CLK_TCON0_CH1 155191#define CLK_TCON1_CH1_SCLK2 156192#define CLK_TCON1_CH1 157193#define CLK_CSI0 158194#define CLK_CSI1 159195#define CLK_CODEC 160196#define CLK_VE 161197#define CLK_AVS 162198#define CLK_ACE 163199#define CLK_HDMI 164200#define CLK_GPU 165201 202#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */203