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1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)2 *3 * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>4 *5 */6 7#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_8#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_9 10#define CLK_CPU 1111 12#define CLK_BUS_DMA 1413#define CLK_BUS_MMC0 1514#define CLK_BUS_MMC1 1615#define CLK_BUS_DRAM 1716#define CLK_BUS_SPI0 1817#define CLK_BUS_SPI1 1918#define CLK_BUS_OTG 2019#define CLK_BUS_VE 2120#define CLK_BUS_LCD 2221#define CLK_BUS_DEINTERLACE 2322#define CLK_BUS_CSI 2423#define CLK_BUS_TVD 2524#define CLK_BUS_TVE 2625#define CLK_BUS_DE_BE 2726#define CLK_BUS_DE_FE 2827#define CLK_BUS_CODEC 2928#define CLK_BUS_SPDIF 3029#define CLK_BUS_IR 3130#define CLK_BUS_RSB 3231#define CLK_BUS_I2S0 3332#define CLK_BUS_I2C0 3433#define CLK_BUS_I2C1 3534#define CLK_BUS_I2C2 3635#define CLK_BUS_PIO 3736#define CLK_BUS_UART0 3837#define CLK_BUS_UART1 3938#define CLK_BUS_UART2 4039 40#define CLK_MMC0 4141#define CLK_MMC0_SAMPLE 4242#define CLK_MMC0_OUTPUT 4343#define CLK_MMC1 4444#define CLK_MMC1_SAMPLE 4545#define CLK_MMC1_OUTPUT 4646#define CLK_I2S 4747#define CLK_SPDIF 4848 49#define CLK_USB_PHY0 4950 51#define CLK_DRAM_VE 5052#define CLK_DRAM_CSI 5153#define CLK_DRAM_DEINTERLACE 5254#define CLK_DRAM_TVD 5355#define CLK_DRAM_DE_FE 5456#define CLK_DRAM_DE_BE 5557 58#define CLK_DE_BE 5659#define CLK_DE_FE 5760#define CLK_TCON 5861#define CLK_DEINTERLACE 5962#define CLK_TVE2_CLK 6063#define CLK_TVE1_CLK 6164#define CLK_TVD 6265#define CLK_CSI 6366#define CLK_VE 6467#define CLK_CODEC 6568#define CLK_AVS 6669 70#define CLK_IR 6771 72#endif73