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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This header provides constants for binding nvidia,tegra114-car.4 *5 * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB6 * registers. These IDs often match those in the CAR's RST_DEVICES registers,7 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In8 * this case, those clocks are assigned IDs above 160 in order to highlight9 * this issue. Implementations that interpret these clock IDs as bit values10 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to11 * explicitly handle these special cases.12 *13 * The balance of the clocks controlled by the CAR are assigned IDs of 160 and14 * above.15 */16 17#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H18#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H19 20/* 0 */21/* 1 */22/* 2 */23/* 3 */24#define TEGRA114_CLK_RTC 425#define TEGRA114_CLK_TIMER 526#define TEGRA114_CLK_UARTA 627/* 7 (register bit affects uartb and vfir) */28/* 8 */29#define TEGRA114_CLK_SDMMC2 930/* 10 (register bit affects spdif_in and spdif_out) */31#define TEGRA114_CLK_I2S1 1132#define TEGRA114_CLK_I2C1 1233#define TEGRA114_CLK_NDFLASH 1334#define TEGRA114_CLK_SDMMC1 1435#define TEGRA114_CLK_SDMMC4 1536/* 16 */37#define TEGRA114_CLK_PWM 1738#define TEGRA114_CLK_I2S2 1839#define TEGRA114_CLK_EPP 1940/* 20 (register bit affects vi and vi_sensor) */41#define TEGRA114_CLK_GR2D 2142#define TEGRA114_CLK_USBD 2243#define TEGRA114_CLK_ISP 2344#define TEGRA114_CLK_GR3D 2445/* 25 */46#define TEGRA114_CLK_DISP2 2647#define TEGRA114_CLK_DISP1 2748#define TEGRA114_CLK_HOST1X 2849#define TEGRA114_CLK_VCP 2950#define TEGRA114_CLK_I2S0 3051/* 31 */52 53#define TEGRA114_CLK_MC 3254/* 33 */55#define TEGRA114_CLK_APBDMA 3456/* 35 */57#define TEGRA114_CLK_KBC 3658/* 37 */59/* 38 */60/* 39 (register bit affects fuse and fuse_burn) */61#define TEGRA114_CLK_KFUSE 4062#define TEGRA114_CLK_SBC1 4163#define TEGRA114_CLK_NOR 4264/* 43 */65#define TEGRA114_CLK_SBC2 4466/* 45 */67#define TEGRA114_CLK_SBC3 4668#define TEGRA114_CLK_I2C5 4769#define TEGRA114_CLK_DSIA 4870/* 49 */71#define TEGRA114_CLK_MIPI 5072#define TEGRA114_CLK_HDMI 5173#define TEGRA114_CLK_CSI 5274/* 53 */75#define TEGRA114_CLK_I2C2 5476#define TEGRA114_CLK_UARTC 5577#define TEGRA114_CLK_MIPI_CAL 5678#define TEGRA114_CLK_EMC 5779#define TEGRA114_CLK_USB2 5880#define TEGRA114_CLK_USB3 5981/* 60 */82#define TEGRA114_CLK_VDE 6183#define TEGRA114_CLK_BSEA 6284#define TEGRA114_CLK_BSEV 6385 86/* 64 */87#define TEGRA114_CLK_UARTD 6588/* 66 */89#define TEGRA114_CLK_I2C3 6790#define TEGRA114_CLK_SBC4 6891#define TEGRA114_CLK_SDMMC3 6992/* 70 */93#define TEGRA114_CLK_OWR 7194/* 72 */95#define TEGRA114_CLK_CSITE 7396/* 74 */97/* 75 */98#define TEGRA114_CLK_LA 7699#define TEGRA114_CLK_TRACE 77100#define TEGRA114_CLK_SOC_THERM 78101#define TEGRA114_CLK_DTV 79102#define TEGRA114_CLK_NDSPEED 80103#define TEGRA114_CLK_I2CSLOW 81104#define TEGRA114_CLK_DSIB 82105#define TEGRA114_CLK_TSEC 83106/* 84 */107/* 85 */108/* 86 */109/* 87 */110/* 88 */111#define TEGRA114_CLK_XUSB_HOST 89112/* 90 */113#define TEGRA114_CLK_MSENC 91114#define TEGRA114_CLK_CSUS 92115/* 93 */116/* 94 */117/* 95 (bit affects xusb_dev and xusb_dev_src) */118 119/* 96 */120/* 97 */121/* 98 */122#define TEGRA114_CLK_MSELECT 99123#define TEGRA114_CLK_TSENSOR 100124#define TEGRA114_CLK_I2S3 101125#define TEGRA114_CLK_I2S4 102126#define TEGRA114_CLK_I2C4 103127#define TEGRA114_CLK_SBC5 104128#define TEGRA114_CLK_SBC6 105129#define TEGRA114_CLK_D_AUDIO 106130#define TEGRA114_CLK_APBIF 107131#define TEGRA114_CLK_DAM0 108132#define TEGRA114_CLK_DAM1 109133#define TEGRA114_CLK_DAM2 110134#define TEGRA114_CLK_HDA2CODEC_2X 111135/* 112 */136#define TEGRA114_CLK_AUDIO0_2X 113137#define TEGRA114_CLK_AUDIO1_2X 114138#define TEGRA114_CLK_AUDIO2_2X 115139#define TEGRA114_CLK_AUDIO3_2X 116140#define TEGRA114_CLK_AUDIO4_2X 117141#define TEGRA114_CLK_SPDIF_2X 118142#define TEGRA114_CLK_ACTMON 119143#define TEGRA114_CLK_EXTERN1 120144#define TEGRA114_CLK_EXTERN2 121145#define TEGRA114_CLK_EXTERN3 122146/* 123 */147/* 124 */148#define TEGRA114_CLK_HDA 125149/* 126 */150#define TEGRA114_CLK_SE 127151 152#define TEGRA114_CLK_HDA2HDMI 128153/* 129 */154/* 130 */155/* 131 */156/* 132 */157/* 133 */158/* 134 */159/* 135 */160#define TEGRA114_CLK_CEC 136161/* 137 */162/* 138 */163/* 139 */164/* 140 */165/* 141 */166/* 142 */167/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */168/* xusb_host_src and xusb_ss_src) */169#define TEGRA114_CLK_CILAB 144170#define TEGRA114_CLK_CILCD 145171#define TEGRA114_CLK_CILE 146172#define TEGRA114_CLK_DSIALP 147173#define TEGRA114_CLK_DSIBLP 148174/* 149 */175#define TEGRA114_CLK_DDS 150176/* 151 */177#define TEGRA114_CLK_DP2 152178#define TEGRA114_CLK_AMX 153179#define TEGRA114_CLK_ADX 154180/* 155 (bit affects dfll_ref and dfll_soc) */181#define TEGRA114_CLK_XUSB_SS 156182/* 157 */183/* 158 */184/* 159 */185 186/* 160 */187/* 161 */188/* 162 */189/* 163 */190/* 164 */191/* 165 */192/* 166 */193/* 167 */194/* 168 */195/* 169 */196/* 170 */197/* 171 */198/* 172 */199/* 173 */200/* 174 */201/* 175 */202/* 176 */203/* 177 */204/* 178 */205/* 179 */206/* 180 */207/* 181 */208/* 182 */209/* 183 */210/* 184 */211/* 185 */212/* 186 */213/* 187 */214/* 188 */215/* 189 */216/* 190 */217/* 191 */218 219#define TEGRA114_CLK_UARTB 192220#define TEGRA114_CLK_VFIR 193221#define TEGRA114_CLK_SPDIF_IN 194222#define TEGRA114_CLK_SPDIF_OUT 195223#define TEGRA114_CLK_VI 196224#define TEGRA114_CLK_VI_SENSOR 197225#define TEGRA114_CLK_FUSE 198226#define TEGRA114_CLK_FUSE_BURN 199227#define TEGRA114_CLK_CLK_32K 200228#define TEGRA114_CLK_CLK_M 201229#define TEGRA114_CLK_CLK_M_DIV2 202230#define TEGRA114_CLK_CLK_M_DIV4 203231#define TEGRA114_CLK_OSC_DIV2 202232#define TEGRA114_CLK_OSC_DIV4 203233#define TEGRA114_CLK_PLL_REF 204234#define TEGRA114_CLK_PLL_C 205235#define TEGRA114_CLK_PLL_C_OUT1 206236#define TEGRA114_CLK_PLL_C2 207237#define TEGRA114_CLK_PLL_C3 208238#define TEGRA114_CLK_PLL_M 209239#define TEGRA114_CLK_PLL_M_OUT1 210240#define TEGRA114_CLK_PLL_P 211241#define TEGRA114_CLK_PLL_P_OUT1 212242#define TEGRA114_CLK_PLL_P_OUT2 213243#define TEGRA114_CLK_PLL_P_OUT3 214244#define TEGRA114_CLK_PLL_P_OUT4 215245#define TEGRA114_CLK_PLL_A 216246#define TEGRA114_CLK_PLL_A_OUT0 217247#define TEGRA114_CLK_PLL_D 218248#define TEGRA114_CLK_PLL_D_OUT0 219249#define TEGRA114_CLK_PLL_D2 220250#define TEGRA114_CLK_PLL_D2_OUT0 221251#define TEGRA114_CLK_PLL_U 222252#define TEGRA114_CLK_PLL_U_480M 223253 254#define TEGRA114_CLK_PLL_U_60M 224255#define TEGRA114_CLK_PLL_U_48M 225256#define TEGRA114_CLK_PLL_U_12M 226257#define TEGRA114_CLK_PLL_X 227258#define TEGRA114_CLK_PLL_X_OUT0 228259#define TEGRA114_CLK_PLL_RE_VCO 229260#define TEGRA114_CLK_PLL_RE_OUT 230261#define TEGRA114_CLK_PLL_E_OUT0 231262#define TEGRA114_CLK_SPDIF_IN_SYNC 232263#define TEGRA114_CLK_I2S0_SYNC 233264#define TEGRA114_CLK_I2S1_SYNC 234265#define TEGRA114_CLK_I2S2_SYNC 235266#define TEGRA114_CLK_I2S3_SYNC 236267#define TEGRA114_CLK_I2S4_SYNC 237268#define TEGRA114_CLK_VIMCLK_SYNC 238269#define TEGRA114_CLK_AUDIO0 239270#define TEGRA114_CLK_AUDIO1 240271#define TEGRA114_CLK_AUDIO2 241272#define TEGRA114_CLK_AUDIO3 242273#define TEGRA114_CLK_AUDIO4 243274#define TEGRA114_CLK_SPDIF 244275/* 245 */276/* 246 */277/* 247 */278/* 248 */279#define TEGRA114_CLK_OSC 249280/* 250 */281/* 251 */282#define TEGRA114_CLK_XUSB_HOST_SRC 252283#define TEGRA114_CLK_XUSB_FALCON_SRC 253284#define TEGRA114_CLK_XUSB_FS_SRC 254285#define TEGRA114_CLK_XUSB_SS_SRC 255286 287#define TEGRA114_CLK_XUSB_DEV_SRC 256288#define TEGRA114_CLK_XUSB_DEV 257289#define TEGRA114_CLK_XUSB_HS_SRC 258290#define TEGRA114_CLK_SCLK 259291#define TEGRA114_CLK_HCLK 260292#define TEGRA114_CLK_PCLK 261293#define TEGRA114_CLK_CCLK_G 262294#define TEGRA114_CLK_CCLK_LP 263295#define TEGRA114_CLK_DFLL_REF 264296#define TEGRA114_CLK_DFLL_SOC 265297/* 266 */298/* 267 */299/* 268 */300/* 269 */301/* 270 */302/* 271 */303/* 272 */304/* 273 */305/* 274 */306/* 275 */307/* 276 */308/* 277 */309/* 278 */310/* 279 */311/* 280 */312/* 281 */313/* 282 */314/* 283 */315/* 284 */316/* 285 */317/* 286 */318/* 287 */319 320/* 288 */321/* 289 */322/* 290 */323/* 291 */324/* 292 */325/* 293 */326/* 294 */327/* 295 */328/* 296 */329/* 297 */330/* 298 */331/* 299 */332#define TEGRA114_CLK_AUDIO0_MUX 300333#define TEGRA114_CLK_AUDIO1_MUX 301334#define TEGRA114_CLK_AUDIO2_MUX 302335#define TEGRA114_CLK_AUDIO3_MUX 303336#define TEGRA114_CLK_AUDIO4_MUX 304337#define TEGRA114_CLK_SPDIF_MUX 305338/* 306 */339/* 307 */340/* 308 */341#define TEGRA114_CLK_DSIA_MUX 309342#define TEGRA114_CLK_DSIB_MUX 310343#define TEGRA114_CLK_XUSB_SS_DIV2 311344#define TEGRA114_CLK_CLK_MAX 312345 346#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */347