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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This header provides constants for binding nvidia,tegra124-car or4 * nvidia,tegra132-car.5 *6 * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB7 * registers. These IDs often match those in the CAR's RST_DEVICES registers,8 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In9 * this case, those clocks are assigned IDs above 185 in order to highlight10 * this issue. Implementations that interpret these clock IDs as bit values11 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to12 * explicitly handle these special cases.13 *14 * The balance of the clocks controlled by the CAR are assigned IDs of 185 and15 * above.16 */17 18#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H19#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H20 21/* 0 */22/* 1 */23/* 2 */24#define TEGRA124_CLK_ISPB 325#define TEGRA124_CLK_RTC 426#define TEGRA124_CLK_TIMER 527#define TEGRA124_CLK_UARTA 628/* 7 (register bit affects uartb and vfir) */29/* 8 */30#define TEGRA124_CLK_SDMMC2 931/* 10 (register bit affects spdif_in and spdif_out) */32#define TEGRA124_CLK_I2S1 1133#define TEGRA124_CLK_I2C1 1234/* 13 */35#define TEGRA124_CLK_SDMMC1 1436#define TEGRA124_CLK_SDMMC4 1537/* 16 */38#define TEGRA124_CLK_PWM 1739#define TEGRA124_CLK_I2S2 1840/* 20 (register bit affects vi and vi_sensor) */41/* 21 */42#define TEGRA124_CLK_USBD 2243#define TEGRA124_CLK_ISP 2344/* 26 */45/* 25 */46#define TEGRA124_CLK_DISP2 2647#define TEGRA124_CLK_DISP1 2748#define TEGRA124_CLK_HOST1X 2849#define TEGRA124_CLK_VCP 2950#define TEGRA124_CLK_I2S0 3051/* 31 */52 53#define TEGRA124_CLK_MC 3254/* 33 */55#define TEGRA124_CLK_APBDMA 3456/* 35 */57#define TEGRA124_CLK_KBC 3658/* 37 */59/* 38 */60/* 39 (register bit affects fuse and fuse_burn) */61#define TEGRA124_CLK_KFUSE 4062#define TEGRA124_CLK_SBC1 4163#define TEGRA124_CLK_NOR 4264/* 43 */65#define TEGRA124_CLK_SBC2 4466/* 45 */67#define TEGRA124_CLK_SBC3 4668#define TEGRA124_CLK_I2C5 4769#define TEGRA124_CLK_DSIA 4870/* 49 */71#define TEGRA124_CLK_MIPI 5072#define TEGRA124_CLK_HDMI 5173#define TEGRA124_CLK_CSI 5274/* 53 */75#define TEGRA124_CLK_I2C2 5476#define TEGRA124_CLK_UARTC 5577#define TEGRA124_CLK_MIPI_CAL 5678#define TEGRA124_CLK_EMC 5779#define TEGRA124_CLK_USB2 5880#define TEGRA124_CLK_USB3 5981/* 60 */82#define TEGRA124_CLK_VDE 6183#define TEGRA124_CLK_BSEA 6284#define TEGRA124_CLK_BSEV 6385 86/* 64 */87#define TEGRA124_CLK_UARTD 6588/* 66 */89#define TEGRA124_CLK_I2C3 6790#define TEGRA124_CLK_SBC4 6891#define TEGRA124_CLK_SDMMC3 6992#define TEGRA124_CLK_PCIE 7093#define TEGRA124_CLK_OWR 7194#define TEGRA124_CLK_AFI 7295#define TEGRA124_CLK_CSITE 7396/* 74 */97/* 75 */98#define TEGRA124_CLK_LA 7699#define TEGRA124_CLK_TRACE 77100#define TEGRA124_CLK_SOC_THERM 78101#define TEGRA124_CLK_DTV 79102/* 80 */103#define TEGRA124_CLK_I2CSLOW 81104#define TEGRA124_CLK_DSIB 82105#define TEGRA124_CLK_TSEC 83106/* 84 */107/* 85 */108/* 86 */109/* 87 */110/* 88 */111#define TEGRA124_CLK_XUSB_HOST 89112/* 90 */113#define TEGRA124_CLK_MSENC 91114#define TEGRA124_CLK_CSUS 92115/* 93 */116/* 94 */117/* 95 (bit affects xusb_dev and xusb_dev_src) */118 119/* 96 */120/* 97 */121/* 98 */122#define TEGRA124_CLK_MSELECT 99123#define TEGRA124_CLK_TSENSOR 100124#define TEGRA124_CLK_I2S3 101125#define TEGRA124_CLK_I2S4 102126#define TEGRA124_CLK_I2C4 103127#define TEGRA124_CLK_SBC5 104128#define TEGRA124_CLK_SBC6 105129#define TEGRA124_CLK_D_AUDIO 106130#define TEGRA124_CLK_APBIF 107131#define TEGRA124_CLK_DAM0 108132#define TEGRA124_CLK_DAM1 109133#define TEGRA124_CLK_DAM2 110134#define TEGRA124_CLK_HDA2CODEC_2X 111135/* 112 */136#define TEGRA124_CLK_AUDIO0_2X 113137#define TEGRA124_CLK_AUDIO1_2X 114138#define TEGRA124_CLK_AUDIO2_2X 115139#define TEGRA124_CLK_AUDIO3_2X 116140#define TEGRA124_CLK_AUDIO4_2X 117141#define TEGRA124_CLK_SPDIF_2X 118142#define TEGRA124_CLK_ACTMON 119143#define TEGRA124_CLK_EXTERN1 120144#define TEGRA124_CLK_EXTERN2 121145#define TEGRA124_CLK_EXTERN3 122146#define TEGRA124_CLK_SATA_OOB 123147#define TEGRA124_CLK_SATA 124148#define TEGRA124_CLK_HDA 125149/* 126 */150#define TEGRA124_CLK_SE 127151 152#define TEGRA124_CLK_HDA2HDMI 128153#define TEGRA124_CLK_SATA_COLD 129154/* 130 */155/* 131 */156/* 132 */157/* 133 */158/* 134 */159/* 135 */160#define TEGRA124_CLK_CEC 136161/* 137 */162/* 138 */163/* 139 */164/* 140 */165/* 141 */166/* 142 */167/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */168/* xusb_host_src and xusb_ss_src) */169#define TEGRA124_CLK_CILAB 144170#define TEGRA124_CLK_CILCD 145171#define TEGRA124_CLK_CILE 146172#define TEGRA124_CLK_DSIALP 147173#define TEGRA124_CLK_DSIBLP 148174#define TEGRA124_CLK_ENTROPY 149175#define TEGRA124_CLK_DDS 150176/* 151 */177#define TEGRA124_CLK_DP2 152178#define TEGRA124_CLK_AMX 153179#define TEGRA124_CLK_ADX 154180/* 155 (bit affects dfll_ref and dfll_soc) */181#define TEGRA124_CLK_XUSB_SS 156182/* 157 */183/* 158 */184/* 159 */185 186/* 160 */187/* 161 */188/* 162 */189/* 163 */190/* 164 */191/* 165 */192#define TEGRA124_CLK_I2C6 166193/* 167 */194/* 168 */195/* 169 */196/* 170 */197#define TEGRA124_CLK_VIM2_CLK 171198/* 172 */199/* 173 */200/* 174 */201/* 175 */202#define TEGRA124_CLK_HDMI_AUDIO 176203#define TEGRA124_CLK_CLK72MHZ 177204#define TEGRA124_CLK_VIC03 178205/* 179 */206#define TEGRA124_CLK_ADX1 180207#define TEGRA124_CLK_DPAUX 181208#define TEGRA124_CLK_SOR0 182209/* 183 */210#define TEGRA124_CLK_GPU 184211#define TEGRA124_CLK_AMX1 185212/* 186 */213/* 187 */214/* 188 */215/* 189 */216/* 190 */217/* 191 */218#define TEGRA124_CLK_UARTB 192219#define TEGRA124_CLK_VFIR 193220#define TEGRA124_CLK_SPDIF_IN 194221#define TEGRA124_CLK_SPDIF_OUT 195222#define TEGRA124_CLK_VI 196223#define TEGRA124_CLK_VI_SENSOR 197224#define TEGRA124_CLK_FUSE 198225#define TEGRA124_CLK_FUSE_BURN 199226#define TEGRA124_CLK_CLK_32K 200227#define TEGRA124_CLK_CLK_M 201228#define TEGRA124_CLK_CLK_M_DIV2 202229#define TEGRA124_CLK_CLK_M_DIV4 203230#define TEGRA124_CLK_OSC_DIV2 202231#define TEGRA124_CLK_OSC_DIV4 203232#define TEGRA124_CLK_PLL_REF 204233#define TEGRA124_CLK_PLL_C 205234#define TEGRA124_CLK_PLL_C_OUT1 206235#define TEGRA124_CLK_PLL_C2 207236#define TEGRA124_CLK_PLL_C3 208237#define TEGRA124_CLK_PLL_M 209238#define TEGRA124_CLK_PLL_M_OUT1 210239#define TEGRA124_CLK_PLL_P 211240#define TEGRA124_CLK_PLL_P_OUT1 212241#define TEGRA124_CLK_PLL_P_OUT2 213242#define TEGRA124_CLK_PLL_P_OUT3 214243#define TEGRA124_CLK_PLL_P_OUT4 215244#define TEGRA124_CLK_PLL_A 216245#define TEGRA124_CLK_PLL_A_OUT0 217246#define TEGRA124_CLK_PLL_D 218247#define TEGRA124_CLK_PLL_D_OUT0 219248#define TEGRA124_CLK_PLL_D2 220249#define TEGRA124_CLK_PLL_D2_OUT0 221250#define TEGRA124_CLK_PLL_U 222251#define TEGRA124_CLK_PLL_U_480M 223252 253#define TEGRA124_CLK_PLL_U_60M 224254#define TEGRA124_CLK_PLL_U_48M 225255#define TEGRA124_CLK_PLL_U_12M 226256/* 227 */257/* 228 */258#define TEGRA124_CLK_PLL_RE_VCO 229259#define TEGRA124_CLK_PLL_RE_OUT 230260#define TEGRA124_CLK_PLL_E 231261#define TEGRA124_CLK_SPDIF_IN_SYNC 232262#define TEGRA124_CLK_I2S0_SYNC 233263#define TEGRA124_CLK_I2S1_SYNC 234264#define TEGRA124_CLK_I2S2_SYNC 235265#define TEGRA124_CLK_I2S3_SYNC 236266#define TEGRA124_CLK_I2S4_SYNC 237267#define TEGRA124_CLK_VIMCLK_SYNC 238268#define TEGRA124_CLK_AUDIO0 239269#define TEGRA124_CLK_AUDIO1 240270#define TEGRA124_CLK_AUDIO2 241271#define TEGRA124_CLK_AUDIO3 242272#define TEGRA124_CLK_AUDIO4 243273#define TEGRA124_CLK_SPDIF 244274/* 245 */275/* 246 */276/* 247 */277/* 248 */278#define TEGRA124_CLK_OSC 249279/* 250 */280/* 251 */281#define TEGRA124_CLK_XUSB_HOST_SRC 252282#define TEGRA124_CLK_XUSB_FALCON_SRC 253283#define TEGRA124_CLK_XUSB_FS_SRC 254284#define TEGRA124_CLK_XUSB_SS_SRC 255285 286#define TEGRA124_CLK_XUSB_DEV_SRC 256287#define TEGRA124_CLK_XUSB_DEV 257288#define TEGRA124_CLK_XUSB_HS_SRC 258289#define TEGRA124_CLK_SCLK 259290#define TEGRA124_CLK_HCLK 260291#define TEGRA124_CLK_PCLK 261292/* 262 */293/* 263 */294#define TEGRA124_CLK_DFLL_REF 264295#define TEGRA124_CLK_DFLL_SOC 265296#define TEGRA124_CLK_VI_SENSOR2 266297#define TEGRA124_CLK_PLL_P_OUT5 267298#define TEGRA124_CLK_CML0 268299#define TEGRA124_CLK_CML1 269300#define TEGRA124_CLK_PLL_C4 270301#define TEGRA124_CLK_PLL_DP 271302#define TEGRA124_CLK_PLL_E_MUX 272303#define TEGRA124_CLK_PLL_D_DSI_OUT 273304/* 274 */305/* 275 */306/* 276 */307/* 277 */308/* 278 */309/* 279 */310/* 280 */311/* 281 */312/* 282 */313/* 283 */314/* 284 */315/* 285 */316/* 286 */317/* 287 */318 319/* 288 */320/* 289 */321/* 290 */322/* 291 */323/* 292 */324/* 293 */325/* 294 */326/* 295 */327/* 296 */328/* 297 */329/* 298 */330/* 299 */331#define TEGRA124_CLK_AUDIO0_MUX 300332#define TEGRA124_CLK_AUDIO1_MUX 301333#define TEGRA124_CLK_AUDIO2_MUX 302334#define TEGRA124_CLK_AUDIO3_MUX 303335#define TEGRA124_CLK_AUDIO4_MUX 304336#define TEGRA124_CLK_SPDIF_MUX 305337/* 306 */338/* 307 */339/* 308 */340/* 309 */341/* 310 */342#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */343#define TEGRA124_CLK_SOR0_OUT 311344#define TEGRA124_CLK_XUSB_SS_DIV2 312345 346#define TEGRA124_CLK_PLL_M_UD 313347#define TEGRA124_CLK_PLL_C_UD 314348 349#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */350