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1/* SPDX-License-Identifier: GPL-2.0 */2/** @file */3 4#ifndef _MACH_T186_CLK_T186_H5#define _MACH_T186_CLK_T186_H6 7/**8 * @defgroup clock_ids Clock Identifiers9 * @{10 * @defgroup extern_input external input clocks11 * @{12 * @def TEGRA186_CLK_OSC13 * @def TEGRA186_CLK_CLK_32K14 * @def TEGRA186_CLK_DTV_INPUT15 * @def TEGRA186_CLK_SOR0_PAD_CLKOUT16 * @def TEGRA186_CLK_SOR1_PAD_CLKOUT17 * @def TEGRA186_CLK_I2S1_SYNC_INPUT18 * @def TEGRA186_CLK_I2S2_SYNC_INPUT19 * @def TEGRA186_CLK_I2S3_SYNC_INPUT20 * @def TEGRA186_CLK_I2S4_SYNC_INPUT21 * @def TEGRA186_CLK_I2S5_SYNC_INPUT22 * @def TEGRA186_CLK_I2S6_SYNC_INPUT23 * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT24 * @}25 *26 * @defgroup extern_output external output clocks27 * @{28 * @def TEGRA186_CLK_EXTPERIPH129 * @def TEGRA186_CLK_EXTPERIPH230 * @def TEGRA186_CLK_EXTPERIPH331 * @def TEGRA186_CLK_EXTPERIPH432 * @}33 *34 * @defgroup display_clks display related clocks35 * @{36 * @def TEGRA186_CLK_CEC37 * @def TEGRA186_CLK_DSIC38 * @def TEGRA186_CLK_DSIC_LP39 * @def TEGRA186_CLK_DSID40 * @def TEGRA186_CLK_DSID_LP41 * @def TEGRA186_CLK_DPAUX142 * @def TEGRA186_CLK_DPAUX43 * @def TEGRA186_CLK_HDA2HDMICODEC44 * @def TEGRA186_CLK_NVDISPLAY_DISP45 * @def TEGRA186_CLK_NVDISPLAY_DSC46 * @def TEGRA186_CLK_NVDISPLAY_P047 * @def TEGRA186_CLK_NVDISPLAY_P148 * @def TEGRA186_CLK_NVDISPLAY_P249 * @def TEGRA186_CLK_NVDISPLAYHUB50 * @def TEGRA186_CLK_SOR_SAFE51 * @def TEGRA186_CLK_SOR052 * @def TEGRA186_CLK_SOR0_OUT53 * @def TEGRA186_CLK_SOR154 * @def TEGRA186_CLK_SOR1_OUT55 * @def TEGRA186_CLK_DSI56 * @def TEGRA186_CLK_MIPI_CAL57 * @def TEGRA186_CLK_DSIA_LP58 * @def TEGRA186_CLK_DSIB59 * @def TEGRA186_CLK_DSIB_LP60 * @}61 *62 * @defgroup camera_clks camera related clocks63 * @{64 * @def TEGRA186_CLK_NVCSI65 * @def TEGRA186_CLK_NVCSILP66 * @def TEGRA186_CLK_VI67 * @}68 *69 * @defgroup audio_clks audio related clocks70 * @{71 * @def TEGRA186_CLK_ACLK72 * @def TEGRA186_CLK_ADSP73 * @def TEGRA186_CLK_ADSPNEON74 * @def TEGRA186_CLK_AHUB75 * @def TEGRA186_CLK_APE76 * @def TEGRA186_CLK_APB2APE77 * @def TEGRA186_CLK_AUD_MCLK78 * @def TEGRA186_CLK_DMIC179 * @def TEGRA186_CLK_DMIC280 * @def TEGRA186_CLK_DMIC381 * @def TEGRA186_CLK_DMIC482 * @def TEGRA186_CLK_DSPK183 * @def TEGRA186_CLK_DSPK284 * @def TEGRA186_CLK_HDA85 * @def TEGRA186_CLK_HDA2CODEC_2X86 * @def TEGRA186_CLK_I2S187 * @def TEGRA186_CLK_I2S288 * @def TEGRA186_CLK_I2S389 * @def TEGRA186_CLK_I2S490 * @def TEGRA186_CLK_I2S591 * @def TEGRA186_CLK_I2S692 * @def TEGRA186_CLK_MAUD93 * @def TEGRA186_CLK_PLL_A_OUT094 * @def TEGRA186_CLK_SPDIF_DOUBLER95 * @def TEGRA186_CLK_SPDIF_IN96 * @def TEGRA186_CLK_SPDIF_OUT97 * @def TEGRA186_CLK_SYNC_DMIC198 * @def TEGRA186_CLK_SYNC_DMIC299 * @def TEGRA186_CLK_SYNC_DMIC3100 * @def TEGRA186_CLK_SYNC_DMIC4101 * @def TEGRA186_CLK_SYNC_DMIC5102 * @def TEGRA186_CLK_SYNC_DSPK1103 * @def TEGRA186_CLK_SYNC_DSPK2104 * @def TEGRA186_CLK_SYNC_I2S1105 * @def TEGRA186_CLK_SYNC_I2S2106 * @def TEGRA186_CLK_SYNC_I2S3107 * @def TEGRA186_CLK_SYNC_I2S4108 * @def TEGRA186_CLK_SYNC_I2S5109 * @def TEGRA186_CLK_SYNC_I2S6110 * @def TEGRA186_CLK_SYNC_SPDIF111 * @}112 *113 * @defgroup uart_clks UART clocks114 * @{115 * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL116 * @def TEGRA186_CLK_UARTA117 * @def TEGRA186_CLK_UARTB118 * @def TEGRA186_CLK_UARTC119 * @def TEGRA186_CLK_UARTD120 * @def TEGRA186_CLK_UARTE121 * @def TEGRA186_CLK_UARTF122 * @def TEGRA186_CLK_UARTG123 * @def TEGRA186_CLK_UART_FST_MIPI_CAL124 * @}125 *126 * @defgroup i2c_clks I2C clocks127 * @{128 * @def TEGRA186_CLK_AON_I2C_SLOW129 * @def TEGRA186_CLK_I2C1130 * @def TEGRA186_CLK_I2C2131 * @def TEGRA186_CLK_I2C3132 * @def TEGRA186_CLK_I2C4133 * @def TEGRA186_CLK_I2C5134 * @def TEGRA186_CLK_I2C6135 * @def TEGRA186_CLK_I2C8136 * @def TEGRA186_CLK_I2C9137 * @def TEGRA186_CLK_I2C1138 * @def TEGRA186_CLK_I2C12139 * @def TEGRA186_CLK_I2C13140 * @def TEGRA186_CLK_I2C14141 * @def TEGRA186_CLK_I2C_SLOW142 * @def TEGRA186_CLK_VI_I2C143 * @}144 *145 * @defgroup spi_clks SPI clocks146 * @{147 * @def TEGRA186_CLK_SPI1148 * @def TEGRA186_CLK_SPI2149 * @def TEGRA186_CLK_SPI3150 * @def TEGRA186_CLK_SPI4151 * @}152 *153 * @defgroup storage storage related clocks154 * @{155 * @def TEGRA186_CLK_SATA156 * @def TEGRA186_CLK_SATA_OOB157 * @def TEGRA186_CLK_SATA_IOBIST158 * @def TEGRA186_CLK_SDMMC_LEGACY_TM159 * @def TEGRA186_CLK_SDMMC1160 * @def TEGRA186_CLK_SDMMC2161 * @def TEGRA186_CLK_SDMMC3162 * @def TEGRA186_CLK_SDMMC4163 * @def TEGRA186_CLK_QSPI164 * @def TEGRA186_CLK_QSPI_OUT165 * @def TEGRA186_CLK_UFSDEV_REF166 * @def TEGRA186_CLK_UFSHC167 * @}168 *169 * @defgroup pwm_clks PWM clocks170 * @{171 * @def TEGRA186_CLK_PWM1172 * @def TEGRA186_CLK_PWM2173 * @def TEGRA186_CLK_PWM3174 * @def TEGRA186_CLK_PWM4175 * @def TEGRA186_CLK_PWM5176 * @def TEGRA186_CLK_PWM6177 * @def TEGRA186_CLK_PWM7178 * @def TEGRA186_CLK_PWM8179 * @}180 *181 * @defgroup plls PLLs and related clocks182 * @{183 * @def TEGRA186_CLK_PLLREFE_OUT_GATED184 * @def TEGRA186_CLK_PLLREFE_OUT1185 * @def TEGRA186_CLK_PLLD_OUT1186 * @def TEGRA186_CLK_PLLP_OUT0187 * @def TEGRA186_CLK_PLLP_OUT5188 * @def TEGRA186_CLK_PLLA189 * @def TEGRA186_CLK_PLLE_PWRSEQ190 * @def TEGRA186_CLK_PLLA_OUT1191 * @def TEGRA186_CLK_PLLREFE_REF192 * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ193 * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ194 * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH195 * @def TEGRA186_CLK_PLLREFE_PEX196 * @def TEGRA186_CLK_PLLREFE_IDDQ197 * @def TEGRA186_CLK_PLLC_OUT_AON198 * @def TEGRA186_CLK_PLLC_OUT_ISP199 * @def TEGRA186_CLK_PLLC_OUT_VE200 * @def TEGRA186_CLK_PLLC4_OUT201 * @def TEGRA186_CLK_PLLREFE_OUT202 * @def TEGRA186_CLK_PLLREFE_PLL_REF203 * @def TEGRA186_CLK_PLLE204 * @def TEGRA186_CLK_PLLC205 * @def TEGRA186_CLK_PLLP206 * @def TEGRA186_CLK_PLLD207 * @def TEGRA186_CLK_PLLD2208 * @def TEGRA186_CLK_PLLREFE_VCO209 * @def TEGRA186_CLK_PLLC2210 * @def TEGRA186_CLK_PLLC3211 * @def TEGRA186_CLK_PLLDP212 * @def TEGRA186_CLK_PLLC4_VCO213 * @def TEGRA186_CLK_PLLA1214 * @def TEGRA186_CLK_PLLNVCSI215 * @def TEGRA186_CLK_PLLDISPHUB216 * @def TEGRA186_CLK_PLLD3217 * @def TEGRA186_CLK_PLLBPMPCAM218 * @def TEGRA186_CLK_PLLAON219 * @def TEGRA186_CLK_PLLU220 * @def TEGRA186_CLK_PLLC4_VCO_DIV2221 * @def TEGRA186_CLK_PLL_REF222 * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5223 * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ224 * @def TEGRA186_CLK_PLL_U_48M225 * @def TEGRA186_CLK_PLL_U_480M226 * @def TEGRA186_CLK_PLLC4_OUT0227 * @def TEGRA186_CLK_PLLC4_OUT1228 * @def TEGRA186_CLK_PLLC4_OUT2229 * @def TEGRA186_CLK_PLLC4_OUT_MUX230 * @def TEGRA186_CLK_DFLLDISP_DIV231 * @def TEGRA186_CLK_PLLDISPHUB_DIV232 * @def TEGRA186_CLK_PLLP_DIV8233 * @}234 *235 * @defgroup nafll_clks NAFLL clock sources236 * @{237 * @def TEGRA186_CLK_NAFLL_AXI_CBB238 * @def TEGRA186_CLK_NAFLL_BCPU239 * @def TEGRA186_CLK_NAFLL_BPMP240 * @def TEGRA186_CLK_NAFLL_DISP241 * @def TEGRA186_CLK_NAFLL_GPU242 * @def TEGRA186_CLK_NAFLL_ISP243 * @def TEGRA186_CLK_NAFLL_MCPU244 * @def TEGRA186_CLK_NAFLL_NVDEC245 * @def TEGRA186_CLK_NAFLL_NVENC246 * @def TEGRA186_CLK_NAFLL_NVJPG247 * @def TEGRA186_CLK_NAFLL_SCE248 * @def TEGRA186_CLK_NAFLL_SE249 * @def TEGRA186_CLK_NAFLL_TSEC250 * @def TEGRA186_CLK_NAFLL_TSECB251 * @def TEGRA186_CLK_NAFLL_VI252 * @def TEGRA186_CLK_NAFLL_VIC253 * @}254 *255 * @defgroup mphy MPHY related clocks256 * @{257 * @def TEGRA186_CLK_MPHY_L0_RX_SYMB258 * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT259 * @def TEGRA186_CLK_MPHY_L0_TX_SYMB260 * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT261 * @def TEGRA186_CLK_MPHY_L0_RX_ANA262 * @def TEGRA186_CLK_MPHY_L1_RX_ANA263 * @def TEGRA186_CLK_MPHY_IOBIST264 * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF265 * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED266 * @}267 *268 * @defgroup eavb EAVB related clocks269 * @{270 * @def TEGRA186_CLK_EQOS_AXI271 * @def TEGRA186_CLK_EQOS_PTP_REF272 * @def TEGRA186_CLK_EQOS_RX273 * @def TEGRA186_CLK_EQOS_RX_INPUT274 * @def TEGRA186_CLK_EQOS_TX275 * @}276 *277 * @defgroup usb USB related clocks278 * @{279 * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT280 * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT281 * @def TEGRA186_CLK_HSIC_TRK282 * @def TEGRA186_CLK_USB2_TRK283 * @def TEGRA186_CLK_USB2_HSIC_TRK284 * @def TEGRA186_CLK_XUSB_CORE_SS285 * @def TEGRA186_CLK_XUSB_CORE_DEV286 * @def TEGRA186_CLK_XUSB_FALCON287 * @def TEGRA186_CLK_XUSB_FS288 * @def TEGRA186_CLK_XUSB289 * @def TEGRA186_CLK_XUSB_DEV290 * @def TEGRA186_CLK_XUSB_HOST291 * @def TEGRA186_CLK_XUSB_SS292 * @}293 *294 * @defgroup bigblock compute block related clocks295 * @{296 * @def TEGRA186_CLK_GPCCLK297 * @def TEGRA186_CLK_GPC2CLK298 * @def TEGRA186_CLK_GPU299 * @def TEGRA186_CLK_HOST1X300 * @def TEGRA186_CLK_ISP301 * @def TEGRA186_CLK_NVDEC302 * @def TEGRA186_CLK_NVENC303 * @def TEGRA186_CLK_NVJPG304 * @def TEGRA186_CLK_SE305 * @def TEGRA186_CLK_TSEC306 * @def TEGRA186_CLK_TSECB307 * @def TEGRA186_CLK_VIC308 * @}309 *310 * @defgroup can CAN bus related clocks311 * @{312 * @def TEGRA186_CLK_CAN1313 * @def TEGRA186_CLK_CAN1_HOST314 * @def TEGRA186_CLK_CAN2315 * @def TEGRA186_CLK_CAN2_HOST316 * @}317 *318 * @defgroup system basic system clocks319 * @{320 * @def TEGRA186_CLK_ACTMON321 * @def TEGRA186_CLK_AON_APB322 * @def TEGRA186_CLK_AON_CPU_NIC323 * @def TEGRA186_CLK_AON_NIC324 * @def TEGRA186_CLK_AXI_CBB325 * @def TEGRA186_CLK_BPMP_APB326 * @def TEGRA186_CLK_BPMP_CPU_NIC327 * @def TEGRA186_CLK_BPMP_NIC_RATE328 * @def TEGRA186_CLK_CLK_M329 * @def TEGRA186_CLK_EMC330 * @def TEGRA186_CLK_MSS_ENCRYPT331 * @def TEGRA186_CLK_SCE_APB332 * @def TEGRA186_CLK_SCE_CPU_NIC333 * @def TEGRA186_CLK_SCE_NIC334 * @def TEGRA186_CLK_TSC335 * @}336 *337 * @defgroup pcie_clks PCIe related clocks338 * @{339 * @def TEGRA186_CLK_AFI340 * @def TEGRA186_CLK_PCIE341 * @def TEGRA186_CLK_PCIE2_IOBIST342 * @def TEGRA186_CLK_PCIERX0343 * @def TEGRA186_CLK_PCIERX1344 * @def TEGRA186_CLK_PCIERX2345 * @def TEGRA186_CLK_PCIERX3346 * @def TEGRA186_CLK_PCIERX4347 * @}348 */349 350/** @brief output of gate CLK_ENB_FUSE */351#define TEGRA186_CLK_FUSE 0352/**353 * @brief It's not what you think354 * @details output of gate CLK_ENB_GPU. This output connects to the GPU355 * pwrclk. @warning: This is almost certainly not the clock you think356 * it is. If you're looking for the clock of the graphics engine, see357 * TEGRA186_GPCCLK358 */359#define TEGRA186_CLK_GPU 1360/** @brief output of gate CLK_ENB_PCIE */361#define TEGRA186_CLK_PCIE 3362/** @brief output of the divider IPFS_CLK_DIVISOR */363#define TEGRA186_CLK_AFI 4364/** @brief output of gate CLK_ENB_PCIE2_IOBIST */365#define TEGRA186_CLK_PCIE2_IOBIST 5366/** @brief output of gate CLK_ENB_PCIERX0*/367#define TEGRA186_CLK_PCIERX0 6368/** @brief output of gate CLK_ENB_PCIERX1*/369#define TEGRA186_CLK_PCIERX1 7370/** @brief output of gate CLK_ENB_PCIERX2*/371#define TEGRA186_CLK_PCIERX2 8372/** @brief output of gate CLK_ENB_PCIERX3*/373#define TEGRA186_CLK_PCIERX3 9374/** @brief output of gate CLK_ENB_PCIERX4*/375#define TEGRA186_CLK_PCIERX4 10376/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */377#define TEGRA186_CLK_PLLC_OUT_ISP 11378/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */379#define TEGRA186_CLK_PLLC_OUT_VE 12380/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */381#define TEGRA186_CLK_PLLC_OUT_AON 13382/** @brief output of gate CLK_ENB_SOR_SAFE */383#define TEGRA186_CLK_SOR_SAFE 39384/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */385#define TEGRA186_CLK_I2S2 42386/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */387#define TEGRA186_CLK_I2S3 43388/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */389#define TEGRA186_CLK_SPDIF_IN 44390/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */391#define TEGRA186_CLK_SPDIF_DOUBLER 45392/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */393#define TEGRA186_CLK_SPI3 46394/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */395#define TEGRA186_CLK_I2C1 47396/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */397#define TEGRA186_CLK_I2C5 48398/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */399#define TEGRA186_CLK_SPI1 49400/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */401#define TEGRA186_CLK_ISP 50402/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */403#define TEGRA186_CLK_VI 51404/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */405#define TEGRA186_CLK_SDMMC1 52406/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */407#define TEGRA186_CLK_SDMMC2 53408/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */409#define TEGRA186_CLK_SDMMC4 54410/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */411#define TEGRA186_CLK_UARTA 55412/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */413#define TEGRA186_CLK_UARTB 56414/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */415#define TEGRA186_CLK_HOST1X 57416/**417 * @brief controls the EMC clock frequency.418 * @details Doing a clk_set_rate on this clock will select the419 * appropriate clock source, program the source rate and execute a420 * specific sequence to switch to the new clock source for both memory421 * controllers. This can be used to control the balance between memory422 * throughput and memory controller power.423 */424#define TEGRA186_CLK_EMC 58425/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */426#define TEGRA186_CLK_EXTPERIPH4 73427/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */428#define TEGRA186_CLK_SPI4 74429/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */430#define TEGRA186_CLK_I2C3 75431/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */432#define TEGRA186_CLK_SDMMC3 76433/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */434#define TEGRA186_CLK_UARTD 77435/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */436#define TEGRA186_CLK_I2S1 79437/** output of gate CLK_ENB_DTV */438#define TEGRA186_CLK_DTV 80439/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */440#define TEGRA186_CLK_TSEC 81441/** @brief output of gate CLK_ENB_DP2 */442#define TEGRA186_CLK_DP2 82443/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */444#define TEGRA186_CLK_I2S4 84445/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */446#define TEGRA186_CLK_I2S5 85447/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */448#define TEGRA186_CLK_I2C4 86449/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */450#define TEGRA186_CLK_AHUB 87451/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */452#define TEGRA186_CLK_HDA2CODEC_2X 88453/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */454#define TEGRA186_CLK_EXTPERIPH1 89455/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */456#define TEGRA186_CLK_EXTPERIPH2 90457/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */458#define TEGRA186_CLK_EXTPERIPH3 91459/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */460#define TEGRA186_CLK_I2C_SLOW 92461/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */462#define TEGRA186_CLK_SOR1 93463/** @brief output of gate CLK_ENB_CEC */464#define TEGRA186_CLK_CEC 94465/** @brief output of gate CLK_ENB_DPAUX1 */466#define TEGRA186_CLK_DPAUX1 95467/** @brief output of gate CLK_ENB_DPAUX */468#define TEGRA186_CLK_DPAUX 96469/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */470#define TEGRA186_CLK_SOR0 97471/** @brief output of gate CLK_ENB_HDA2HDMICODEC */472#define TEGRA186_CLK_HDA2HDMICODEC 98473/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */474#define TEGRA186_CLK_SATA 99475/** @brief output of gate CLK_ENB_SATA_OOB */476#define TEGRA186_CLK_SATA_OOB 100477/** @brief output of gate CLK_ENB_SATA_IOBIST */478#define TEGRA186_CLK_SATA_IOBIST 101479/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */480#define TEGRA186_CLK_HDA 102481/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */482#define TEGRA186_CLK_SE 103483/** @brief output of gate CLK_ENB_APB2APE */484#define TEGRA186_CLK_APB2APE 104485/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */486#define TEGRA186_CLK_APE 105487/** @brief output of gate CLK_ENB_IQC1 */488#define TEGRA186_CLK_IQC1 106489/** @brief output of gate CLK_ENB_IQC2 */490#define TEGRA186_CLK_IQC2 107491/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */492#define TEGRA186_CLK_PLLREFE_OUT 108493/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */494#define TEGRA186_CLK_PLLREFE_PLL_REF 109495/** @brief output of gate CLK_ENB_PLLC4_OUT */496#define TEGRA186_CLK_PLLC4_OUT 110497/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */498#define TEGRA186_CLK_XUSB 111499/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */500#define TEGRA186_CLK_XUSB_DEV 112501/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */502#define TEGRA186_CLK_XUSB_HOST 113503/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */504#define TEGRA186_CLK_XUSB_SS 114505/** @brief output of gate CLK_ENB_DSI */506#define TEGRA186_CLK_DSI 115507/** @brief output of gate CLK_ENB_MIPI_CAL */508#define TEGRA186_CLK_MIPI_CAL 116509/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */510#define TEGRA186_CLK_DSIA_LP 117511/** @brief output of gate CLK_ENB_DSIB */512#define TEGRA186_CLK_DSIB 118513/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */514#define TEGRA186_CLK_DSIB_LP 119515/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */516#define TEGRA186_CLK_DMIC1 122517/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */518#define TEGRA186_CLK_DMIC2 123519/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */520#define TEGRA186_CLK_AUD_MCLK 124521/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */522#define TEGRA186_CLK_I2C6 125523/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */524#define TEGRA186_CLK_UART_FST_MIPI_CAL 126525/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */526#define TEGRA186_CLK_VIC 127527/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */528#define TEGRA186_CLK_SDMMC_LEGACY_TM 128529/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */530#define TEGRA186_CLK_NVDEC 129531/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */532#define TEGRA186_CLK_NVJPG 130533/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */534#define TEGRA186_CLK_NVENC 131535/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */536#define TEGRA186_CLK_QSPI 132537/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */538#define TEGRA186_CLK_VI_I2C 133539/** @brief output of gate CLK_ENB_HSIC_TRK */540#define TEGRA186_CLK_HSIC_TRK 134541/** @brief output of gate CLK_ENB_USB2_TRK */542#define TEGRA186_CLK_USB2_TRK 135543/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */544#define TEGRA186_CLK_MAUD 136545/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */546#define TEGRA186_CLK_TSECB 137547/** @brief output of gate CLK_ENB_ADSP */548#define TEGRA186_CLK_ADSP 138549/** @brief output of gate CLK_ENB_ADSPNEON */550#define TEGRA186_CLK_ADSPNEON 139551/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */552#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140553/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */554#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141555/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */556#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142557/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */558#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143559/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */560#define TEGRA186_CLK_MPHY_L0_RX_ANA 144561/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */562#define TEGRA186_CLK_MPHY_L1_RX_ANA 145563/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */564#define TEGRA186_CLK_MPHY_IOBIST 146565/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */566#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147567/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */568#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148569/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */570#define TEGRA186_CLK_AXI_CBB 149571/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */572#define TEGRA186_CLK_DMIC3 150573/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */574#define TEGRA186_CLK_DMIC4 151575/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */576#define TEGRA186_CLK_DSPK1 152577/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */578#define TEGRA186_CLK_DSPK2 153579/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */580#define TEGRA186_CLK_I2S6 154581/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */582#define TEGRA186_CLK_NVDISPLAY_P0 155583/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */584#define TEGRA186_CLK_NVDISPLAY_DISP 156585/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */586#define TEGRA186_CLK_NVDISPLAY_DSC 157587/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */588#define TEGRA186_CLK_NVDISPLAYHUB 158589/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */590#define TEGRA186_CLK_NVDISPLAY_P1 159591/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */592#define TEGRA186_CLK_NVDISPLAY_P2 160593/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */594#define TEGRA186_CLK_TACH 166595/** @brief output of gate CLK_ENB_EQOS */596#define TEGRA186_CLK_EQOS_AXI 167597/** @brief output of gate CLK_ENB_EQOS_RX */598#define TEGRA186_CLK_EQOS_RX 168599/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */600#define TEGRA186_CLK_UFSHC 178601/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */602#define TEGRA186_CLK_UFSDEV_REF 179603/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */604#define TEGRA186_CLK_NVCSI 180605/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */606#define TEGRA186_CLK_NVCSILP 181607/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */608#define TEGRA186_CLK_I2C7 182609/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */610#define TEGRA186_CLK_I2C9 183611/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */612#define TEGRA186_CLK_I2C12 184613/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */614#define TEGRA186_CLK_I2C13 185615/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */616#define TEGRA186_CLK_I2C14 186617/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */618#define TEGRA186_CLK_PWM1 187619/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */620#define TEGRA186_CLK_PWM2 188621/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */622#define TEGRA186_CLK_PWM3 189623/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */624#define TEGRA186_CLK_PWM5 190625/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */626#define TEGRA186_CLK_PWM6 191627/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */628#define TEGRA186_CLK_PWM7 192629/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */630#define TEGRA186_CLK_PWM8 193631/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */632#define TEGRA186_CLK_UARTE 194633/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */634#define TEGRA186_CLK_UARTF 195635/** @deprecated */636#define TEGRA186_CLK_DBGAPB 196637/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */638#define TEGRA186_CLK_BPMP_CPU_NIC 197639/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */640#define TEGRA186_CLK_BPMP_APB 199641/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */642#define TEGRA186_CLK_ACTMON 201643/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */644#define TEGRA186_CLK_AON_CPU_NIC 208645/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */646#define TEGRA186_CLK_CAN1 210647/** @brief output of gate CLK_ENB_CAN1_HOST */648#define TEGRA186_CLK_CAN1_HOST 211649/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */650#define TEGRA186_CLK_CAN2 212651/** @brief output of gate CLK_ENB_CAN2_HOST */652#define TEGRA186_CLK_CAN2_HOST 213653/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */654#define TEGRA186_CLK_AON_APB 214655/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */656#define TEGRA186_CLK_UARTC 215657/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */658#define TEGRA186_CLK_UARTG 216659/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */660#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217661/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */662#define TEGRA186_CLK_I2C2 218663/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */664#define TEGRA186_CLK_I2C8 219665/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */666#define TEGRA186_CLK_I2C10 220667/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */668#define TEGRA186_CLK_AON_I2C_SLOW 221669/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */670#define TEGRA186_CLK_SPI2 222671/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */672#define TEGRA186_CLK_DMIC5 223673/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */674#define TEGRA186_CLK_AON_TOUCH 224675/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */676#define TEGRA186_CLK_PWM4 225677/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */678#define TEGRA186_CLK_TSC 226679/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */680#define TEGRA186_CLK_MSS_ENCRYPT 227681/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */682#define TEGRA186_CLK_SCE_CPU_NIC 228683/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */684#define TEGRA186_CLK_SCE_APB 230685/** @brief output of gate CLK_ENB_DSIC */686#define TEGRA186_CLK_DSIC 231687/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */688#define TEGRA186_CLK_DSIC_LP 232689/** @brief output of gate CLK_ENB_DSID */690#define TEGRA186_CLK_DSID 233691/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */692#define TEGRA186_CLK_DSID_LP 234693/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */694#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236695/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */696#define TEGRA186_CLK_SPDIF_OUT 238697/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */698#define TEGRA186_CLK_EQOS_PTP_REF 239699/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */700#define TEGRA186_CLK_EQOS_TX 240701/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */702#define TEGRA186_CLK_USB2_HSIC_TRK 241703/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */704#define TEGRA186_CLK_XUSB_CORE_SS 242705/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */706#define TEGRA186_CLK_XUSB_CORE_DEV 243707/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */708#define TEGRA186_CLK_XUSB_FALCON 244709/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */710#define TEGRA186_CLK_XUSB_FS 245711/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */712#define TEGRA186_CLK_PLL_A_OUT0 246713/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */714#define TEGRA186_CLK_SYNC_I2S1 247715/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */716#define TEGRA186_CLK_SYNC_I2S2 248717/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */718#define TEGRA186_CLK_SYNC_I2S3 249719/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */720#define TEGRA186_CLK_SYNC_I2S4 250721/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */722#define TEGRA186_CLK_SYNC_I2S5 251723/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */724#define TEGRA186_CLK_SYNC_I2S6 252725/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */726#define TEGRA186_CLK_SYNC_DSPK1 253727/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */728#define TEGRA186_CLK_SYNC_DSPK2 254729/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */730#define TEGRA186_CLK_SYNC_DMIC1 255731/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */732#define TEGRA186_CLK_SYNC_DMIC2 256733/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */734#define TEGRA186_CLK_SYNC_DMIC3 257735/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */736#define TEGRA186_CLK_SYNC_DMIC4 259737/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */738#define TEGRA186_CLK_SYNC_SPDIF 260739/** @brief output of gate CLK_ENB_PLLREFE_OUT */740#define TEGRA186_CLK_PLLREFE_OUT_GATED 261741/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:742 * * VCO/pdiv defined by this clock object743 * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT744 */745#define TEGRA186_CLK_PLLREFE_OUT1 262746#define TEGRA186_CLK_PLLD_OUT1 267747/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */748#define TEGRA186_CLK_PLLP_OUT0 269749/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */750#define TEGRA186_CLK_PLLP_OUT5 270751/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */752#define TEGRA186_CLK_PLLA 271753/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */754#define TEGRA186_CLK_ACLK 273755/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */756#define TEGRA186_CLK_PLL_U_48M 274757/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */758#define TEGRA186_CLK_PLL_U_480M 275759/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */760#define TEGRA186_CLK_PLLC4_OUT0 276761/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */762#define TEGRA186_CLK_PLLC4_OUT1 277763/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */764#define TEGRA186_CLK_PLLC4_OUT2 278765/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */766#define TEGRA186_CLK_PLLC4_OUT_MUX 279767/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */768#define TEGRA186_CLK_DFLLDISP_DIV 284769/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */770#define TEGRA186_CLK_PLLDISPHUB_DIV 285771/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */772#define TEGRA186_CLK_PLLP_DIV8 286773/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */774#define TEGRA186_CLK_BPMP_NIC 287775/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */776#define TEGRA186_CLK_PLL_A_OUT1 288777/** @deprecated */778#define TEGRA186_CLK_GPC2CLK 289779/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */780#define TEGRA186_CLK_KFUSE 293781/**782 * @brief controls the PLLE hardware sequencer.783 * @details This clock only has enable and disable methods. When the784 * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by785 * hw based on the control signals from the PCIe, SATA and XUSB786 * clocks. When the PLLE hw sequencer is disabled, the state of PLLE787 * is controlled by sw using clk_enable/clk_disable on788 * TEGRA186_CLK_PLLE.789 */790#define TEGRA186_CLK_PLLE_PWRSEQ 294791/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */792#define TEGRA186_CLK_PLLREFE_REF 295793/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */794#define TEGRA186_CLK_SOR0_OUT 296795/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */796#define TEGRA186_CLK_SOR1_OUT 297797/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */798#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298799/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */800#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301801/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */802#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302803/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */804#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303805/** @brief controls the UPHY_PLL0 hardware sqeuencer */806#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304807/** @brief controls the UPHY_PLL1 hardware sqeuencer */808#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305809/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */810#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306811/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */812#define TEGRA186_CLK_PLLREFE_PEX 307813/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */814#define TEGRA186_CLK_PLLREFE_IDDQ 308815/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */816#define TEGRA186_CLK_QSPI_OUT 309817/**818 * @brief GPC2CLK-div-2819 * @details fixed /2 divider. Output frequency is820 * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the821 * frequency at which the GPU graphics engine runs. */822#define TEGRA186_CLK_GPCCLK 310823/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */824#define TEGRA186_CLK_AON_NIC 450825/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */826#define TEGRA186_CLK_SCE_NIC 451827/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */828#define TEGRA186_CLK_PLLE 512829/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */830#define TEGRA186_CLK_PLLC 513831/** Fixed 408MHz PLL for use by peripheral clocks */832#define TEGRA186_CLK_PLLP 516833/** @deprecated */834#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP835/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */836#define TEGRA186_CLK_PLLD 518837/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */838#define TEGRA186_CLK_PLLD2 519839/**840 * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.841 * @details Note that this clock only controls the VCO output, before842 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more843 * information.844 */845#define TEGRA186_CLK_PLLREFE_VCO 520846/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */847#define TEGRA186_CLK_PLLC2 521848/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */849#define TEGRA186_CLK_PLLC3 522850/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */851#define TEGRA186_CLK_PLLDP 523852/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */853#define TEGRA186_CLK_PLLC4_VCO 524854/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */855#define TEGRA186_CLK_PLLA1 525856/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */857#define TEGRA186_CLK_PLLNVCSI 526858/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */859#define TEGRA186_CLK_PLLDISPHUB 527860/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */861#define TEGRA186_CLK_PLLD3 528862/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */863#define TEGRA186_CLK_PLLBPMPCAM 531864/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */865#define TEGRA186_CLK_PLLAON 532866/** Fixed frequency 960MHz PLL for USB and EAVB */867#define TEGRA186_CLK_PLLU 533868/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */869#define TEGRA186_CLK_PLLC4_VCO_DIV2 535870/** @brief NAFLL clock source for AXI_CBB */871#define TEGRA186_CLK_NAFLL_AXI_CBB 564872/** @brief NAFLL clock source for BPMP */873#define TEGRA186_CLK_NAFLL_BPMP 565874/** @brief NAFLL clock source for ISP */875#define TEGRA186_CLK_NAFLL_ISP 566876/** @brief NAFLL clock source for NVDEC */877#define TEGRA186_CLK_NAFLL_NVDEC 567878/** @brief NAFLL clock source for NVENC */879#define TEGRA186_CLK_NAFLL_NVENC 568880/** @brief NAFLL clock source for NVJPG */881#define TEGRA186_CLK_NAFLL_NVJPG 569882/** @brief NAFLL clock source for SCE */883#define TEGRA186_CLK_NAFLL_SCE 570884/** @brief NAFLL clock source for SE */885#define TEGRA186_CLK_NAFLL_SE 571886/** @brief NAFLL clock source for TSEC */887#define TEGRA186_CLK_NAFLL_TSEC 572888/** @brief NAFLL clock source for TSECB */889#define TEGRA186_CLK_NAFLL_TSECB 573890/** @brief NAFLL clock source for VI */891#define TEGRA186_CLK_NAFLL_VI 574892/** @brief NAFLL clock source for VIC */893#define TEGRA186_CLK_NAFLL_VIC 575894/** @brief NAFLL clock source for DISP */895#define TEGRA186_CLK_NAFLL_DISP 576896/** @brief NAFLL clock source for GPU */897#define TEGRA186_CLK_NAFLL_GPU 577898/** @brief NAFLL clock source for M-CPU cluster */899#define TEGRA186_CLK_NAFLL_MCPU 578900/** @brief NAFLL clock source for B-CPU cluster */901#define TEGRA186_CLK_NAFLL_BCPU 579902/** @brief input from Tegra's CLK_32K_IN pad */903#define TEGRA186_CLK_CLK_32K 608904/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */905#define TEGRA186_CLK_CLK_M 609906/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */907#define TEGRA186_CLK_PLL_REF 610908/** @brief input from Tegra's XTAL_IN */909#define TEGRA186_CLK_OSC 612910/** @brief clock recovered from EAVB input */911#define TEGRA186_CLK_EQOS_RX_INPUT 613912/** @brief clock recovered from DTV input */913#define TEGRA186_CLK_DTV_INPUT 614914/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/915#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615916/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/917#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616918/** @brief clock recovered from I2S1 input */919#define TEGRA186_CLK_I2S1_SYNC_INPUT 617920/** @brief clock recovered from I2S2 input */921#define TEGRA186_CLK_I2S2_SYNC_INPUT 618922/** @brief clock recovered from I2S3 input */923#define TEGRA186_CLK_I2S3_SYNC_INPUT 619924/** @brief clock recovered from I2S4 input */925#define TEGRA186_CLK_I2S4_SYNC_INPUT 620926/** @brief clock recovered from I2S5 input */927#define TEGRA186_CLK_I2S5_SYNC_INPUT 621928/** @brief clock recovered from I2S6 input */929#define TEGRA186_CLK_I2S6_SYNC_INPUT 622930/** @brief clock recovered from SPDIFIN input */931#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623932 933/**934 * @brief subject to change935 * @details maximum clock identifier value plus one.936 */937#define TEGRA186_CLK_CLK_MAX 624938 939/** @} */940 941#endif942