322 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */3 4#ifndef __ABI_MACH_T194_CLOCK_H5#define __ABI_MACH_T194_CLOCK_H6 7#define TEGRA194_CLK_ACTMON 18#define TEGRA194_CLK_ADSP 29#define TEGRA194_CLK_ADSPNEON 310#define TEGRA194_CLK_AHUB 411#define TEGRA194_CLK_APB2APE 512#define TEGRA194_CLK_APE 613#define TEGRA194_CLK_AUD_MCLK 714#define TEGRA194_CLK_AXI_CBB 815#define TEGRA194_CLK_CAN1 916#define TEGRA194_CLK_CAN1_HOST 1017#define TEGRA194_CLK_CAN2 1118#define TEGRA194_CLK_CAN2_HOST 1219#define TEGRA194_CLK_CEC 1320#define TEGRA194_CLK_CLK_M 1421#define TEGRA194_CLK_DMIC1 1522#define TEGRA194_CLK_DMIC2 1623#define TEGRA194_CLK_DMIC3 1724#define TEGRA194_CLK_DMIC4 1825#define TEGRA194_CLK_DPAUX 1926#define TEGRA194_CLK_DPAUX1 2027#define TEGRA194_CLK_ACLK 2128#define TEGRA194_CLK_MSS_ENCRYPT 2229#define TEGRA194_CLK_EQOS_RX_INPUT 2330#define TEGRA194_CLK_IQC2 2431#define TEGRA194_CLK_AON_APB 2532#define TEGRA194_CLK_AON_NIC 2633#define TEGRA194_CLK_AON_CPU_NIC 2734#define TEGRA194_CLK_PLLA1 2835#define TEGRA194_CLK_DSPK1 2936#define TEGRA194_CLK_DSPK2 3037#define TEGRA194_CLK_EMC 3138#define TEGRA194_CLK_EQOS_AXI 3239#define TEGRA194_CLK_EQOS_PTP_REF 3340#define TEGRA194_CLK_EQOS_RX 3441#define TEGRA194_CLK_EQOS_TX 3542#define TEGRA194_CLK_EXTPERIPH1 3643#define TEGRA194_CLK_EXTPERIPH2 3744#define TEGRA194_CLK_EXTPERIPH3 3845#define TEGRA194_CLK_EXTPERIPH4 3946#define TEGRA194_CLK_FUSE 4047#define TEGRA194_CLK_GPCCLK 4148#define TEGRA194_CLK_GPU_PWR 4249#define TEGRA194_CLK_HDA 4350#define TEGRA194_CLK_HDA2CODEC_2X 4451#define TEGRA194_CLK_HDA2HDMICODEC 4552#define TEGRA194_CLK_HOST1X 4653#define TEGRA194_CLK_HSIC_TRK 4754#define TEGRA194_CLK_I2C1 4855#define TEGRA194_CLK_I2C2 4956#define TEGRA194_CLK_I2C3 5057#define TEGRA194_CLK_I2C4 5158#define TEGRA194_CLK_I2C6 5259#define TEGRA194_CLK_I2C7 5360#define TEGRA194_CLK_I2C8 5461#define TEGRA194_CLK_I2C9 5562#define TEGRA194_CLK_I2S1 5663#define TEGRA194_CLK_I2S1_SYNC_INPUT 5764#define TEGRA194_CLK_I2S2 5865#define TEGRA194_CLK_I2S2_SYNC_INPUT 5966#define TEGRA194_CLK_I2S3 6067#define TEGRA194_CLK_I2S3_SYNC_INPUT 6168#define TEGRA194_CLK_I2S4 6269#define TEGRA194_CLK_I2S4_SYNC_INPUT 6370#define TEGRA194_CLK_I2S5 6471#define TEGRA194_CLK_I2S5_SYNC_INPUT 6572#define TEGRA194_CLK_I2S6 6673#define TEGRA194_CLK_I2S6_SYNC_INPUT 6774#define TEGRA194_CLK_IQC1 6875#define TEGRA194_CLK_ISP 6976#define TEGRA194_CLK_KFUSE 7077#define TEGRA194_CLK_MAUD 7178#define TEGRA194_CLK_MIPI_CAL 7279#define TEGRA194_CLK_MPHY_CORE_PLL_FIXED 7380#define TEGRA194_CLK_MPHY_L0_RX_ANA 7481#define TEGRA194_CLK_MPHY_L0_RX_LS_BIT 7582#define TEGRA194_CLK_MPHY_L0_RX_SYMB 7683#define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT 7784#define TEGRA194_CLK_MPHY_L0_TX_SYMB 7885#define TEGRA194_CLK_MPHY_L1_RX_ANA 7986#define TEGRA194_CLK_MPHY_TX_1MHZ_REF 8087#define TEGRA194_CLK_NVCSI 8188#define TEGRA194_CLK_NVCSILP 8289#define TEGRA194_CLK_NVDEC 8390#define TEGRA194_CLK_NVDISPLAYHUB 8491#define TEGRA194_CLK_NVDISPLAY_DISP 8592#define TEGRA194_CLK_NVDISPLAY_P0 8693#define TEGRA194_CLK_NVDISPLAY_P1 8794#define TEGRA194_CLK_NVDISPLAY_P2 8895#define TEGRA194_CLK_NVENC 8996#define TEGRA194_CLK_NVJPG 9097#define TEGRA194_CLK_OSC 9198#define TEGRA194_CLK_AON_TOUCH 9299#define TEGRA194_CLK_PLLA 93100#define TEGRA194_CLK_PLLAON 94101#define TEGRA194_CLK_PLLD 95102#define TEGRA194_CLK_PLLD2 96103#define TEGRA194_CLK_PLLD3 97104#define TEGRA194_CLK_PLLDP 98105#define TEGRA194_CLK_PLLD4 99106#define TEGRA194_CLK_PLLE 100107#define TEGRA194_CLK_PLLP 101108#define TEGRA194_CLK_PLLP_OUT0 102109#define TEGRA194_CLK_UTMIPLL 103110#define TEGRA194_CLK_PLLA_OUT0 104111#define TEGRA194_CLK_PWM1 105112#define TEGRA194_CLK_PWM2 106113#define TEGRA194_CLK_PWM3 107114#define TEGRA194_CLK_PWM4 108115#define TEGRA194_CLK_PWM5 109116#define TEGRA194_CLK_PWM6 110117#define TEGRA194_CLK_PWM7 111118#define TEGRA194_CLK_PWM8 112119#define TEGRA194_CLK_RCE_CPU_NIC 113120#define TEGRA194_CLK_RCE_NIC 114121#define TEGRA194_CLK_SATA 115122#define TEGRA194_CLK_SATA_OOB 116123#define TEGRA194_CLK_AON_I2C_SLOW 117124#define TEGRA194_CLK_SCE_CPU_NIC 118125#define TEGRA194_CLK_SCE_NIC 119126#define TEGRA194_CLK_SDMMC1 120127#define TEGRA194_CLK_UPHY_PLL3 121128#define TEGRA194_CLK_SDMMC3 122129#define TEGRA194_CLK_SDMMC4 123130#define TEGRA194_CLK_SE 124131#define TEGRA194_CLK_SOR0_OUT 125132#define TEGRA194_CLK_SOR0_REF 126133#define TEGRA194_CLK_SOR0_PAD_CLKOUT 127134#define TEGRA194_CLK_SOR1_OUT 128135#define TEGRA194_CLK_SOR1_REF 129136#define TEGRA194_CLK_SOR1_PAD_CLKOUT 130137#define TEGRA194_CLK_SOR_SAFE 131138#define TEGRA194_CLK_IQC1_IN 132139#define TEGRA194_CLK_IQC2_IN 133140#define TEGRA194_CLK_DMIC5 134141#define TEGRA194_CLK_SPI1 135142#define TEGRA194_CLK_SPI2 136143#define TEGRA194_CLK_SPI3 137144#define TEGRA194_CLK_I2C_SLOW 138145#define TEGRA194_CLK_SYNC_DMIC1 139146#define TEGRA194_CLK_SYNC_DMIC2 140147#define TEGRA194_CLK_SYNC_DMIC3 141148#define TEGRA194_CLK_SYNC_DMIC4 142149#define TEGRA194_CLK_SYNC_DSPK1 143150#define TEGRA194_CLK_SYNC_DSPK2 144151#define TEGRA194_CLK_SYNC_I2S1 145152#define TEGRA194_CLK_SYNC_I2S2 146153#define TEGRA194_CLK_SYNC_I2S3 147154#define TEGRA194_CLK_SYNC_I2S4 148155#define TEGRA194_CLK_SYNC_I2S5 149156#define TEGRA194_CLK_SYNC_I2S6 150157#define TEGRA194_CLK_MPHY_FORCE_LS_MODE 151158#define TEGRA194_CLK_TACH 152159#define TEGRA194_CLK_TSEC 153160#define TEGRA194_CLK_TSECB 154161#define TEGRA194_CLK_UARTA 155162#define TEGRA194_CLK_UARTB 156163#define TEGRA194_CLK_UARTC 157164#define TEGRA194_CLK_UARTD 158165#define TEGRA194_CLK_UARTE 159166#define TEGRA194_CLK_UARTF 160167#define TEGRA194_CLK_UARTG 161168#define TEGRA194_CLK_UART_FST_MIPI_CAL 162169#define TEGRA194_CLK_UFSDEV_REF 163170#define TEGRA194_CLK_UFSHC 164171#define TEGRA194_CLK_USB2_TRK 165172#define TEGRA194_CLK_VI 166173#define TEGRA194_CLK_VIC 167174#define TEGRA194_CLK_PVA0_AXI 168175#define TEGRA194_CLK_PVA0_VPS0 169176#define TEGRA194_CLK_PVA0_VPS1 170177#define TEGRA194_CLK_PVA1_AXI 171178#define TEGRA194_CLK_PVA1_VPS0 172179#define TEGRA194_CLK_PVA1_VPS1 173180#define TEGRA194_CLK_DLA0_FALCON 174181#define TEGRA194_CLK_DLA0_CORE 175182#define TEGRA194_CLK_DLA1_FALCON 176183#define TEGRA194_CLK_DLA1_CORE 177184#define TEGRA194_CLK_SOR2_OUT 178185#define TEGRA194_CLK_SOR2_REF 179186#define TEGRA194_CLK_SOR2_PAD_CLKOUT 180187#define TEGRA194_CLK_SOR3_OUT 181188#define TEGRA194_CLK_SOR3_REF 182189#define TEGRA194_CLK_SOR3_PAD_CLKOUT 183190#define TEGRA194_CLK_NVDISPLAY_P3 184191#define TEGRA194_CLK_DPAUX2 185192#define TEGRA194_CLK_DPAUX3 186193#define TEGRA194_CLK_NVDEC1 187194#define TEGRA194_CLK_NVENC1 188195#define TEGRA194_CLK_SE_FREE 189196#define TEGRA194_CLK_UARTH 190197#define TEGRA194_CLK_FUSE_SERIAL 191198#define TEGRA194_CLK_QSPI0 192199#define TEGRA194_CLK_QSPI1 193200#define TEGRA194_CLK_QSPI0_PM 194201#define TEGRA194_CLK_QSPI1_PM 195202#define TEGRA194_CLK_VI_CONST 196203#define TEGRA194_CLK_NAFLL_BPMP 197204#define TEGRA194_CLK_NAFLL_SCE 198205#define TEGRA194_CLK_NAFLL_NVDEC 199206#define TEGRA194_CLK_NAFLL_NVJPG 200207#define TEGRA194_CLK_NAFLL_TSEC 201208#define TEGRA194_CLK_NAFLL_TSECB 202209#define TEGRA194_CLK_NAFLL_VI 203210#define TEGRA194_CLK_NAFLL_SE 204211#define TEGRA194_CLK_NAFLL_NVENC 205212#define TEGRA194_CLK_NAFLL_ISP 206213#define TEGRA194_CLK_NAFLL_VIC 207214#define TEGRA194_CLK_NAFLL_NVDISPLAYHUB 208215#define TEGRA194_CLK_NAFLL_AXICBB 209216#define TEGRA194_CLK_NAFLL_DLA 210217#define TEGRA194_CLK_NAFLL_PVA_CORE 211218#define TEGRA194_CLK_NAFLL_PVA_VPS 212219#define TEGRA194_CLK_NAFLL_CVNAS 213220#define TEGRA194_CLK_NAFLL_RCE 214221#define TEGRA194_CLK_NAFLL_NVENC1 215222#define TEGRA194_CLK_NAFLL_DLA_FALCON 216223#define TEGRA194_CLK_NAFLL_NVDEC1 217224#define TEGRA194_CLK_NAFLL_GPU 218225#define TEGRA194_CLK_SDMMC_LEGACY_TM 219226#define TEGRA194_CLK_PEX0_CORE_0 220227#define TEGRA194_CLK_PEX0_CORE_1 221228#define TEGRA194_CLK_PEX0_CORE_2 222229#define TEGRA194_CLK_PEX0_CORE_3 223230#define TEGRA194_CLK_PEX0_CORE_4 224231#define TEGRA194_CLK_PEX1_CORE_5 225232#define TEGRA194_CLK_PEX_REF1 226233#define TEGRA194_CLK_PEX_REF2 227234#define TEGRA194_CLK_CSI_A 229235#define TEGRA194_CLK_CSI_B 230236#define TEGRA194_CLK_CSI_C 231237#define TEGRA194_CLK_CSI_D 232238#define TEGRA194_CLK_CSI_E 233239#define TEGRA194_CLK_CSI_F 234240#define TEGRA194_CLK_CSI_G 235241#define TEGRA194_CLK_CSI_H 236242#define TEGRA194_CLK_PLLC4 237243#define TEGRA194_CLK_PLLC4_OUT 238244#define TEGRA194_CLK_PLLC4_OUT1 239245#define TEGRA194_CLK_PLLC4_OUT2 240246#define TEGRA194_CLK_PLLC4_MUXED 241247#define TEGRA194_CLK_PLLC4_VCO_DIV2 242248#define TEGRA194_CLK_CSI_A_PAD 244249#define TEGRA194_CLK_CSI_B_PAD 245250#define TEGRA194_CLK_CSI_C_PAD 246251#define TEGRA194_CLK_CSI_D_PAD 247252#define TEGRA194_CLK_CSI_E_PAD 248253#define TEGRA194_CLK_CSI_F_PAD 249254#define TEGRA194_CLK_CSI_G_PAD 250255#define TEGRA194_CLK_CSI_H_PAD 251256#define TEGRA194_CLK_PEX_SATA_USB_RX_BYP 254257#define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT 255258#define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT 256259#define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT 257260#define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT 258261#define TEGRA194_CLK_XUSB_CORE_DEV 265262#define TEGRA194_CLK_XUSB_CORE_MUX 266263#define TEGRA194_CLK_XUSB_CORE_HOST 267264#define TEGRA194_CLK_XUSB_CORE_SS 268265#define TEGRA194_CLK_XUSB_FALCON 269266#define TEGRA194_CLK_XUSB_FALCON_HOST 270267#define TEGRA194_CLK_XUSB_FALCON_SS 271268#define TEGRA194_CLK_XUSB_FS 272269#define TEGRA194_CLK_XUSB_FS_HOST 273270#define TEGRA194_CLK_XUSB_FS_DEV 274271#define TEGRA194_CLK_XUSB_SS 275272#define TEGRA194_CLK_XUSB_SS_DEV 276273#define TEGRA194_CLK_XUSB_SS_SUPERSPEED 277274#define TEGRA194_CLK_PLLDISPHUB 278275#define TEGRA194_CLK_PLLDISPHUB_DIV 279276#define TEGRA194_CLK_NAFLL_CLUSTER0 280277#define TEGRA194_CLK_NAFLL_CLUSTER1 281278#define TEGRA194_CLK_NAFLL_CLUSTER2 282279#define TEGRA194_CLK_NAFLL_CLUSTER3 283280#define TEGRA194_CLK_CAN1_CORE 284281#define TEGRA194_CLK_CAN2_CORE 285282#define TEGRA194_CLK_PLLA1_OUT1 286283#define TEGRA194_CLK_PLLREFE_VCOOUT 288284#define TEGRA194_CLK_CLK_32K 289285#define TEGRA194_CLK_SPDIFIN_SYNC_INPUT 290286#define TEGRA194_CLK_UTMIPLL_CLKOUT48 291287#define TEGRA194_CLK_UTMIPLL_CLKOUT480 292288#define TEGRA194_CLK_CVNAS 293289#define TEGRA194_CLK_PLLNVCSI 294290#define TEGRA194_CLK_PVA0_CPU_AXI 295291#define TEGRA194_CLK_PVA1_CPU_AXI 296292#define TEGRA194_CLK_PVA0_VPS 297293#define TEGRA194_CLK_PVA1_VPS 298294#define TEGRA194_CLK_DLA0_FALCON_MUX 299295#define TEGRA194_CLK_DLA1_FALCON_MUX 300296#define TEGRA194_CLK_DLA0_CORE_MUX 301297#define TEGRA194_CLK_DLA1_CORE_MUX 302298#define TEGRA194_CLK_UTMIPLL_HPS 304299#define TEGRA194_CLK_I2C5 305300#define TEGRA194_CLK_I2C10 306301#define TEGRA194_CLK_BPMP_CPU_NIC 307302#define TEGRA194_CLK_BPMP_APB 308303#define TEGRA194_CLK_TSC 309304#define TEGRA194_CLK_EMCSA 310305#define TEGRA194_CLK_EMCSB 311306#define TEGRA194_CLK_EMCSC 312307#define TEGRA194_CLK_EMCSD 313308#define TEGRA194_CLK_PLLC 314309#define TEGRA194_CLK_PLLC2 315310#define TEGRA194_CLK_PLLC3 316311#define TEGRA194_CLK_TSC_REF 317312#define TEGRA194_CLK_FUSE_BURN 318313#define TEGRA194_CLK_PEX0_CORE_0M 319314#define TEGRA194_CLK_PEX0_CORE_1M 320315#define TEGRA194_CLK_PEX0_CORE_2M 321316#define TEGRA194_CLK_PEX0_CORE_3M 322317#define TEGRA194_CLK_PEX0_CORE_4M 323318#define TEGRA194_CLK_PEX1_CORE_5M 324319#define TEGRA194_CLK_PLLE_HPS 326320 321#endif322