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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This header provides constants for binding nvidia,tegra20-car.4 *5 * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB6 * registers. These IDs often match those in the CAR's RST_DEVICES registers,7 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In8 * this case, those clocks are assigned IDs above 95 in order to highlight9 * this issue. Implementations that interpret these clock IDs as bit values10 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to11 * explicitly handle these special cases.12 *13 * The balance of the clocks controlled by the CAR are assigned IDs of 96 and14 * above.15 */16 17#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H18#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H19 20#define TEGRA20_CLK_CPU 021/* 1 */22/* 2 */23#define TEGRA20_CLK_AC97 324#define TEGRA20_CLK_RTC 425#define TEGRA20_CLK_TIMER 526#define TEGRA20_CLK_UARTA 627/* 7 (register bit affects uart2 and vfir) */28#define TEGRA20_CLK_GPIO 829#define TEGRA20_CLK_SDMMC2 930/* 10 (register bit affects spdif_in and spdif_out) */31#define TEGRA20_CLK_I2S1 1132#define TEGRA20_CLK_I2C1 1233#define TEGRA20_CLK_NDFLASH 1334#define TEGRA20_CLK_SDMMC1 1435#define TEGRA20_CLK_SDMMC4 1536#define TEGRA20_CLK_TWC 1637#define TEGRA20_CLK_PWM 1738#define TEGRA20_CLK_I2S2 1839#define TEGRA20_CLK_EPP 1940/* 20 (register bit affects vi and vi_sensor) */41#define TEGRA20_CLK_GR2D 2142#define TEGRA20_CLK_USBD 2243#define TEGRA20_CLK_ISP 2344#define TEGRA20_CLK_GR3D 2445#define TEGRA20_CLK_IDE 2546#define TEGRA20_CLK_DISP2 2647#define TEGRA20_CLK_DISP1 2748#define TEGRA20_CLK_HOST1X 2849#define TEGRA20_CLK_VCP 2950/* 30 */51#define TEGRA20_CLK_CACHE2 3152 53#define TEGRA20_CLK_MC 3254#define TEGRA20_CLK_AHBDMA 3355#define TEGRA20_CLK_APBDMA 3456/* 35 */57#define TEGRA20_CLK_KBC 3658#define TEGRA20_CLK_STAT_MON 3759#define TEGRA20_CLK_PMC 3860#define TEGRA20_CLK_FUSE 3961#define TEGRA20_CLK_KFUSE 4062#define TEGRA20_CLK_SBC1 4163#define TEGRA20_CLK_NOR 4264#define TEGRA20_CLK_SPI 4365#define TEGRA20_CLK_SBC2 4466#define TEGRA20_CLK_XIO 4567#define TEGRA20_CLK_SBC3 4668#define TEGRA20_CLK_DVC 4769#define TEGRA20_CLK_DSI 4870/* 49 (register bit affects tvo and cve) */71#define TEGRA20_CLK_MIPI 5072#define TEGRA20_CLK_HDMI 5173#define TEGRA20_CLK_CSI 5274#define TEGRA20_CLK_TVDAC 5375#define TEGRA20_CLK_I2C2 5476#define TEGRA20_CLK_UARTC 5577/* 56 */78#define TEGRA20_CLK_EMC 5779#define TEGRA20_CLK_USB2 5880#define TEGRA20_CLK_USB3 5981#define TEGRA20_CLK_MPE 6082#define TEGRA20_CLK_VDE 6183#define TEGRA20_CLK_BSEA 6284#define TEGRA20_CLK_BSEV 6385 86#define TEGRA20_CLK_SPEEDO 6487#define TEGRA20_CLK_UARTD 6588#define TEGRA20_CLK_UARTE 6689#define TEGRA20_CLK_I2C3 6790#define TEGRA20_CLK_SBC4 6891#define TEGRA20_CLK_SDMMC3 6992#define TEGRA20_CLK_PEX 7093#define TEGRA20_CLK_OWR 7194#define TEGRA20_CLK_AFI 7295#define TEGRA20_CLK_CSITE 7396/* 74 */97#define TEGRA20_CLK_AVPUCQ 7598#define TEGRA20_CLK_LA 7699/* 77 */100/* 78 */101/* 79 */102/* 80 */103/* 81 */104/* 82 */105/* 83 */106#define TEGRA20_CLK_IRAMA 84107#define TEGRA20_CLK_IRAMB 85108#define TEGRA20_CLK_IRAMC 86109#define TEGRA20_CLK_IRAMD 87110#define TEGRA20_CLK_CRAM2 88111#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */112#define TEGRA20_CLK_CLK_D 90113/* 91 */114#define TEGRA20_CLK_CSUS 92115#define TEGRA20_CLK_CDEV2 93116#define TEGRA20_CLK_CDEV1 94117/* 95 */118 119#define TEGRA20_CLK_UARTB 96120#define TEGRA20_CLK_VFIR 97121#define TEGRA20_CLK_SPDIF_IN 98122#define TEGRA20_CLK_SPDIF_OUT 99123#define TEGRA20_CLK_VI 100124#define TEGRA20_CLK_VI_SENSOR 101125#define TEGRA20_CLK_TVO 102126#define TEGRA20_CLK_CVE 103127#define TEGRA20_CLK_OSC 104128#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */129#define TEGRA20_CLK_CLK_M 106130#define TEGRA20_CLK_SCLK 107131#define TEGRA20_CLK_CCLK 108132#define TEGRA20_CLK_HCLK 109133#define TEGRA20_CLK_PCLK 110134/* 111 */135#define TEGRA20_CLK_PLL_A 112136#define TEGRA20_CLK_PLL_A_OUT0 113137#define TEGRA20_CLK_PLL_C 114138#define TEGRA20_CLK_PLL_C_OUT1 115139#define TEGRA20_CLK_PLL_D 116140#define TEGRA20_CLK_PLL_D_OUT0 117141#define TEGRA20_CLK_PLL_E 118142#define TEGRA20_CLK_PLL_M 119143#define TEGRA20_CLK_PLL_M_OUT1 120144#define TEGRA20_CLK_PLL_P 121145#define TEGRA20_CLK_PLL_P_OUT1 122146#define TEGRA20_CLK_PLL_P_OUT2 123147#define TEGRA20_CLK_PLL_P_OUT3 124148#define TEGRA20_CLK_PLL_P_OUT4 125149#define TEGRA20_CLK_PLL_S 126150#define TEGRA20_CLK_PLL_U 127151 152#define TEGRA20_CLK_PLL_X 128153#define TEGRA20_CLK_COP 129 /* a/k/a avp */154#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */155#define TEGRA20_CLK_PLL_REF 131156#define TEGRA20_CLK_TWD 132157#define TEGRA20_CLK_CLK_MAX 133158 159#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */160