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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This header provides constants for binding nvidia,tegra210-car.4 *5 * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB6 * registers. These IDs often match those in the CAR's RST_DEVICES registers,7 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In8 * this case, those clocks are assigned IDs above 224 in order to highlight9 * this issue. Implementations that interpret these clock IDs as bit values10 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to11 * explicitly handle these special cases.12 *13 * The balance of the clocks controlled by the CAR are assigned IDs of 224 and14 * above.15 */16 17#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H18#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H19 20/* 0 */21/* 1 */22/* 2 */23#define TEGRA210_CLK_ISPB 324#define TEGRA210_CLK_RTC 425#define TEGRA210_CLK_TIMER 526#define TEGRA210_CLK_UARTA 627/* 7 (register bit affects uartb and vfir) */28#define TEGRA210_CLK_GPIO 829#define TEGRA210_CLK_SDMMC2 930/* 10 (register bit affects spdif_in and spdif_out) */31#define TEGRA210_CLK_I2S1 1132#define TEGRA210_CLK_I2C1 1233/* 13 */34#define TEGRA210_CLK_SDMMC1 1435#define TEGRA210_CLK_SDMMC4 1536/* 16 */37#define TEGRA210_CLK_PWM 1738#define TEGRA210_CLK_I2S2 1839/* 19 */40/* 20 (register bit affects vi and vi_sensor) */41/* 21 */42#define TEGRA210_CLK_USBD 2243#define TEGRA210_CLK_ISPA 2344/* 24 */45/* 25 */46#define TEGRA210_CLK_DISP2 2647#define TEGRA210_CLK_DISP1 2748#define TEGRA210_CLK_HOST1X 2849/* 29 */50#define TEGRA210_CLK_I2S0 3051/* 31 */52 53#define TEGRA210_CLK_MC 3254#define TEGRA210_CLK_AHBDMA 3355#define TEGRA210_CLK_APBDMA 3456/* 35 */57/* 36 */58/* 37 */59#define TEGRA210_CLK_PMC 3860/* 39 (register bit affects fuse and fuse_burn) */61#define TEGRA210_CLK_KFUSE 4062#define TEGRA210_CLK_SBC1 4163/* 42 */64/* 43 */65#define TEGRA210_CLK_SBC2 4466/* 45 */67#define TEGRA210_CLK_SBC3 4668#define TEGRA210_CLK_I2C5 4769#define TEGRA210_CLK_DSIA 4870/* 49 */71/* 50 */72/* 51 */73#define TEGRA210_CLK_CSI 5274/* 53 */75#define TEGRA210_CLK_I2C2 5476#define TEGRA210_CLK_UARTC 5577#define TEGRA210_CLK_MIPI_CAL 5678#define TEGRA210_CLK_EMC 5779#define TEGRA210_CLK_USB2 5880/* 59 */81/* 60 */82/* 61 */83/* 62 */84#define TEGRA210_CLK_BSEV 6385 86/* 64 */87#define TEGRA210_CLK_UARTD 6588/* 66 */89#define TEGRA210_CLK_I2C3 6790#define TEGRA210_CLK_SBC4 6891#define TEGRA210_CLK_SDMMC3 6992#define TEGRA210_CLK_PCIE 7093#define TEGRA210_CLK_OWR 7194#define TEGRA210_CLK_AFI 7295#define TEGRA210_CLK_CSITE 7396/* 74 */97/* 75 */98#define TEGRA210_CLK_LA 7699/* 77 */100#define TEGRA210_CLK_SOC_THERM 78101#define TEGRA210_CLK_DTV 79102/* 80 */103#define TEGRA210_CLK_I2CSLOW 81104#define TEGRA210_CLK_DSIB 82105#define TEGRA210_CLK_TSEC 83106/* 84 */107/* 85 */108/* 86 */109/* 87 */110/* 88 */111#define TEGRA210_CLK_XUSB_HOST 89112/* 90 */113/* 91 */114#define TEGRA210_CLK_CSUS 92115/* 93 */116/* 94 */117/* 95 (bit affects xusb_dev and xusb_dev_src) */118 119/* 96 */120/* 97 */121/* 98 */122#define TEGRA210_CLK_MSELECT 99123#define TEGRA210_CLK_TSENSOR 100124#define TEGRA210_CLK_I2S3 101125#define TEGRA210_CLK_I2S4 102126#define TEGRA210_CLK_I2C4 103127/* 104 */128/* 105 */129#define TEGRA210_CLK_D_AUDIO 106130#define TEGRA210_CLK_APB2APE 107131/* 108 */132/* 109 */133/* 110 */134#define TEGRA210_CLK_HDA2CODEC_2X 111135/* 112 */136/* 113 */137/* 114 */138/* 115 */139/* 116 */140/* 117 */141#define TEGRA210_CLK_SPDIF_2X 118142#define TEGRA210_CLK_ACTMON 119143#define TEGRA210_CLK_EXTERN1 120144#define TEGRA210_CLK_EXTERN2 121145#define TEGRA210_CLK_EXTERN3 122146#define TEGRA210_CLK_SATA_OOB 123147#define TEGRA210_CLK_SATA 124148#define TEGRA210_CLK_HDA 125149/* 126 */150/* 127 */151 152#define TEGRA210_CLK_HDA2HDMI 128153/* 129 */154/* 130 */155/* 131 */156/* 132 */157/* 133 */158/* 134 */159/* 135 */160#define TEGRA210_CLK_CEC 136161/* 137 */162/* 138 */163/* 139 */164/* 140 */165/* 141 */166/* 142 */167/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */168#define TEGRA210_CLK_XUSB_GATE 143169#define TEGRA210_CLK_CILAB 144170#define TEGRA210_CLK_CILCD 145171#define TEGRA210_CLK_CILE 146172#define TEGRA210_CLK_DSIALP 147173#define TEGRA210_CLK_DSIBLP 148174#define TEGRA210_CLK_ENTROPY 149175/* 150 */176/* 151 */177#define TEGRA210_CLK_DP2 152178/* 153 */179/* 154 */180/* 155 (bit affects dfll_ref and dfll_soc) */181#define TEGRA210_CLK_XUSB_SS 156182/* 157 */183/* 158 */184/* 159 */185 186/* 160 */187#define TEGRA210_CLK_DMIC1 161188#define TEGRA210_CLK_DMIC2 162189/* 163 */190/* 164 */191/* 165 */192#define TEGRA210_CLK_I2C6 166193/* 167 */194/* 168 */195/* 169 */196/* 170 */197#define TEGRA210_CLK_VIM2_CLK 171198/* 172 */199#define TEGRA210_CLK_MIPIBIF 173200/* 174 */201/* 175 */202/* 176 */203#define TEGRA210_CLK_CLK72MHZ 177204#define TEGRA210_CLK_VIC03 178205/* 179 */206/* 180 */207#define TEGRA210_CLK_DPAUX 181208#define TEGRA210_CLK_SOR0 182209#define TEGRA210_CLK_SOR1 183210#define TEGRA210_CLK_GPU 184211#define TEGRA210_CLK_DBGAPB 185212/* 186 */213#define TEGRA210_CLK_PLL_P_OUT_ADSP 187214/* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/215#define TEGRA210_CLK_PLL_G_REF 189216/* 190 */217/* 191 */218 219/* 192 */220#define TEGRA210_CLK_SDMMC_LEGACY 193221#define TEGRA210_CLK_NVDEC 194222#define TEGRA210_CLK_NVJPG 195223/* 196 */224#define TEGRA210_CLK_DMIC3 197225#define TEGRA210_CLK_APE 198226#define TEGRA210_CLK_ADSP 199227/* 200 */228/* 201 */229#define TEGRA210_CLK_MAUD 202230/* 203 */231/* 204 */232/* 205 */233#define TEGRA210_CLK_TSECB 206234#define TEGRA210_CLK_DPAUX1 207235#define TEGRA210_CLK_VI_I2C 208236#define TEGRA210_CLK_HSIC_TRK 209237#define TEGRA210_CLK_USB2_TRK 210238#define TEGRA210_CLK_QSPI 211239#define TEGRA210_CLK_UARTAPE 212240/* 213 */241/* 214 */242/* 215 */243/* 216 */244/* 217 */245#define TEGRA210_CLK_ADSP_NEON 218246#define TEGRA210_CLK_NVENC 219247#define TEGRA210_CLK_IQC2 220248#define TEGRA210_CLK_IQC1 221249#define TEGRA210_CLK_SOR_SAFE 222250#define TEGRA210_CLK_PLL_P_OUT_CPU 223251 252 253#define TEGRA210_CLK_UARTB 224254#define TEGRA210_CLK_VFIR 225255#define TEGRA210_CLK_SPDIF_IN 226256#define TEGRA210_CLK_SPDIF_OUT 227257#define TEGRA210_CLK_VI 228258#define TEGRA210_CLK_VI_SENSOR 229259#define TEGRA210_CLK_FUSE 230260#define TEGRA210_CLK_FUSE_BURN 231261#define TEGRA210_CLK_CLK_32K 232262#define TEGRA210_CLK_CLK_M 233263#define TEGRA210_CLK_CLK_M_DIV2 234264#define TEGRA210_CLK_CLK_M_DIV4 235265#define TEGRA210_CLK_OSC_DIV2 234266#define TEGRA210_CLK_OSC_DIV4 235267#define TEGRA210_CLK_PLL_REF 236268#define TEGRA210_CLK_PLL_C 237269#define TEGRA210_CLK_PLL_C_OUT1 238270#define TEGRA210_CLK_PLL_C2 239271#define TEGRA210_CLK_PLL_C3 240272#define TEGRA210_CLK_PLL_M 241273#define TEGRA210_CLK_PLL_M_OUT1 242274#define TEGRA210_CLK_PLL_P 243275#define TEGRA210_CLK_PLL_P_OUT1 244276#define TEGRA210_CLK_PLL_P_OUT2 245277#define TEGRA210_CLK_PLL_P_OUT3 246278#define TEGRA210_CLK_PLL_P_OUT4 247279#define TEGRA210_CLK_PLL_A 248280#define TEGRA210_CLK_PLL_A_OUT0 249281#define TEGRA210_CLK_PLL_D 250282#define TEGRA210_CLK_PLL_D_OUT0 251283#define TEGRA210_CLK_PLL_D2 252284#define TEGRA210_CLK_PLL_D2_OUT0 253285#define TEGRA210_CLK_PLL_U 254286#define TEGRA210_CLK_PLL_U_480M 255287 288#define TEGRA210_CLK_PLL_U_60M 256289#define TEGRA210_CLK_PLL_U_48M 257290/* 258 */291#define TEGRA210_CLK_PLL_X 259292#define TEGRA210_CLK_PLL_X_OUT0 260293#define TEGRA210_CLK_PLL_RE_VCO 261294#define TEGRA210_CLK_PLL_RE_OUT 262295#define TEGRA210_CLK_PLL_E 263296#define TEGRA210_CLK_SPDIF_IN_SYNC 264297#define TEGRA210_CLK_I2S0_SYNC 265298#define TEGRA210_CLK_I2S1_SYNC 266299#define TEGRA210_CLK_I2S2_SYNC 267300#define TEGRA210_CLK_I2S3_SYNC 268301#define TEGRA210_CLK_I2S4_SYNC 269302#define TEGRA210_CLK_VIMCLK_SYNC 270303#define TEGRA210_CLK_AUDIO0 271304#define TEGRA210_CLK_AUDIO1 272305#define TEGRA210_CLK_AUDIO2 273306#define TEGRA210_CLK_AUDIO3 274307#define TEGRA210_CLK_AUDIO4 275308#define TEGRA210_CLK_SPDIF 276309/* 277 */310#define TEGRA210_CLK_QSPI_PM 278311/* 279 */312/* 280 */313#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */314#define TEGRA210_CLK_SOR0_OUT 281315#define TEGRA210_CLK_SOR1_OUT 282316/* 283 */317#define TEGRA210_CLK_XUSB_HOST_SRC 284318#define TEGRA210_CLK_XUSB_FALCON_SRC 285319#define TEGRA210_CLK_XUSB_FS_SRC 286320#define TEGRA210_CLK_XUSB_SS_SRC 287321 322#define TEGRA210_CLK_XUSB_DEV_SRC 288323#define TEGRA210_CLK_XUSB_DEV 289324#define TEGRA210_CLK_XUSB_HS_SRC 290325#define TEGRA210_CLK_SCLK 291326#define TEGRA210_CLK_HCLK 292327#define TEGRA210_CLK_PCLK 293328#define TEGRA210_CLK_CCLK_G 294329#define TEGRA210_CLK_CCLK_LP 295330#define TEGRA210_CLK_DFLL_REF 296331#define TEGRA210_CLK_DFLL_SOC 297332#define TEGRA210_CLK_VI_SENSOR2 298333#define TEGRA210_CLK_PLL_P_OUT5 299334#define TEGRA210_CLK_CML0 300335#define TEGRA210_CLK_CML1 301336#define TEGRA210_CLK_PLL_C4 302337#define TEGRA210_CLK_PLL_DP 303338#define TEGRA210_CLK_PLL_E_MUX 304339#define TEGRA210_CLK_PLL_MB 305340#define TEGRA210_CLK_PLL_A1 306341#define TEGRA210_CLK_PLL_D_DSI_OUT 307342#define TEGRA210_CLK_PLL_C4_OUT0 308343#define TEGRA210_CLK_PLL_C4_OUT1 309344#define TEGRA210_CLK_PLL_C4_OUT2 310345#define TEGRA210_CLK_PLL_C4_OUT3 311346#define TEGRA210_CLK_PLL_U_OUT 312347#define TEGRA210_CLK_PLL_U_OUT1 313348#define TEGRA210_CLK_PLL_U_OUT2 314349#define TEGRA210_CLK_USB2_HSIC_TRK 315350#define TEGRA210_CLK_PLL_P_OUT_HSIO 316351#define TEGRA210_CLK_PLL_P_OUT_XUSB 317352#define TEGRA210_CLK_XUSB_SSP_SRC 318353#define TEGRA210_CLK_PLL_RE_OUT1 319354#define TEGRA210_CLK_PLL_MB_UD 320355#define TEGRA210_CLK_PLL_P_UD 321356#define TEGRA210_CLK_ISP 322357#define TEGRA210_CLK_PLL_A_OUT_ADSP 323358#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324359/* 325 */360#define TEGRA210_CLK_OSC 326361#define TEGRA210_CLK_CSI_TPG 327362/* 328 */363/* 329 */364/* 330 */365/* 331 */366/* 332 */367/* 333 */368/* 334 */369/* 335 */370/* 336 */371/* 337 */372/* 338 */373/* 339 */374/* 340 */375/* 341 */376/* 342 */377/* 343 */378/* 344 */379/* 345 */380/* 346 */381/* 347 */382/* 348 */383/* 349 */384 385#define TEGRA210_CLK_AUDIO0_MUX 350386#define TEGRA210_CLK_AUDIO1_MUX 351387#define TEGRA210_CLK_AUDIO2_MUX 352388#define TEGRA210_CLK_AUDIO3_MUX 353389#define TEGRA210_CLK_AUDIO4_MUX 354390#define TEGRA210_CLK_SPDIF_MUX 355391/* 356 */392/* 357 */393/* 358 */394#define TEGRA210_CLK_DSIA_MUX 359395#define TEGRA210_CLK_DSIB_MUX 360396/* 361 */397#define TEGRA210_CLK_XUSB_SS_DIV2 362398 399#define TEGRA210_CLK_PLL_M_UD 363400#define TEGRA210_CLK_PLL_C_UD 364401#define TEGRA210_CLK_SCLK_MUX 365402 403#define TEGRA210_CLK_ACLK 370404 405#define TEGRA210_CLK_DMIC1_SYNC_CLK 388406#define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389407#define TEGRA210_CLK_DMIC2_SYNC_CLK 390408#define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391409#define TEGRA210_CLK_DMIC3_SYNC_CLK 392410#define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393411 412#define TEGRA210_CLK_CLK_MAX 394413 414#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */415