904 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */3 4#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H5#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H6 7/**8 * @file9 * @defgroup bpmp_clock_ids Clock ID's10 * @{11 */12/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */13#define TEGRA234_CLK_ACTMON 1U14/** @brief output of gate CLK_ENB_ADSP */15#define TEGRA234_CLK_ADSP 2U16/** @brief output of gate CLK_ENB_ADSPNEON */17#define TEGRA234_CLK_ADSPNEON 3U18/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */19#define TEGRA234_CLK_AHUB 4U20/** @brief output of gate CLK_ENB_APB2APE */21#define TEGRA234_CLK_APB2APE 5U22/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */23#define TEGRA234_CLK_APE 6U24/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */25#define TEGRA234_CLK_AUD_MCLK 7U26/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */27#define TEGRA234_CLK_AXI_CBB 8U28/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */29#define TEGRA234_CLK_CAN1 9U30/** @brief output of gate CLK_ENB_CAN1_HOST */31#define TEGRA234_CLK_CAN1_HOST 10U32/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */33#define TEGRA234_CLK_CAN2 11U34/** @brief output of gate CLK_ENB_CAN2_HOST */35#define TEGRA234_CLK_CAN2_HOST 12U36/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */37#define TEGRA234_CLK_CLK_M 14U38/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */39#define TEGRA234_CLK_DMIC1 15U40/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */41#define TEGRA234_CLK_DMIC2 16U42/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */43#define TEGRA234_CLK_DMIC3 17U44/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */45#define TEGRA234_CLK_DMIC4 18U46/** @brief output of gate CLK_ENB_DPAUX */47#define TEGRA234_CLK_DPAUX 19U48/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG1 */49#define TEGRA234_CLK_NVJPG1 20U50/**51 * @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY52 * divided by the divider controlled by ACLK_CLK_DIVISOR in53 * CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER54 */55#define TEGRA234_CLK_ACLK 21U56/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */57#define TEGRA234_CLK_MSS_ENCRYPT 22U58/** @brief clock recovered from EAVB input */59#define TEGRA234_CLK_EQOS_RX_INPUT 23U60/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */61#define TEGRA234_CLK_AON_APB 25U62/** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */63#define TEGRA234_CLK_AON_NIC 26U64/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */65#define TEGRA234_CLK_AON_CPU_NIC 27U66/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */67#define TEGRA234_CLK_PLLA1 28U68/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */69#define TEGRA234_CLK_DSPK1 29U70/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */71#define TEGRA234_CLK_DSPK2 30U72/**73 * @brief controls the EMC clock frequency.74 * @details Doing a clk_set_rate on this clock will select the75 * appropriate clock source, program the source rate and execute a76 * specific sequence to switch to the new clock source for both memory77 * controllers. This can be used to control the balance between memory78 * throughput and memory controller power.79 */80#define TEGRA234_CLK_EMC 31U81/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */82#define TEGRA234_CLK_EQOS_AXI 32U83/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */84#define TEGRA234_CLK_EQOS_PTP_REF 33U85/** @brief output of gate CLK_ENB_EQOS_RX */86#define TEGRA234_CLK_EQOS_RX 34U87/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */88#define TEGRA234_CLK_EQOS_TX 35U89/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */90#define TEGRA234_CLK_EXTPERIPH1 36U91/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */92#define TEGRA234_CLK_EXTPERIPH2 37U93/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */94#define TEGRA234_CLK_EXTPERIPH3 38U95/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */96#define TEGRA234_CLK_EXTPERIPH4 39U97/** @brief output of gate CLK_ENB_FUSE */98#define TEGRA234_CLK_FUSE 40U99/** @brief output of GPU GPC0 clkGen (in 1x mode same rate as GPC0 MUX2 out) */100#define TEGRA234_CLK_GPC0CLK 41U101/** @brief TODO */102#define TEGRA234_CLK_GPU_PWR 42U103/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */104/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */105#define TEGRA234_CLK_HOST1X 46U106/** @brief xusb_hs_hsicp_clk */107#define TEGRA234_CLK_XUSB_HS_HSICP 47U108/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */109#define TEGRA234_CLK_I2C1 48U110/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */111#define TEGRA234_CLK_I2C2 49U112/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */113#define TEGRA234_CLK_I2C3 50U114/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */115#define TEGRA234_CLK_I2C4 51U116/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */117#define TEGRA234_CLK_I2C6 52U118/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */119#define TEGRA234_CLK_I2C7 53U120/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */121#define TEGRA234_CLK_I2C8 54U122/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */123#define TEGRA234_CLK_I2C9 55U124/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */125#define TEGRA234_CLK_I2S1 56U126/** @brief clock recovered from I2S1 input */127#define TEGRA234_CLK_I2S1_SYNC_INPUT 57U128/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */129#define TEGRA234_CLK_I2S2 58U130/** @brief clock recovered from I2S2 input */131#define TEGRA234_CLK_I2S2_SYNC_INPUT 59U132/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */133#define TEGRA234_CLK_I2S3 60U134/** @brief clock recovered from I2S3 input */135#define TEGRA234_CLK_I2S3_SYNC_INPUT 61U136/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */137#define TEGRA234_CLK_I2S4 62U138/** @brief clock recovered from I2S4 input */139#define TEGRA234_CLK_I2S4_SYNC_INPUT 63U140/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */141#define TEGRA234_CLK_I2S5 64U142/** @brief clock recovered from I2S5 input */143#define TEGRA234_CLK_I2S5_SYNC_INPUT 65U144/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */145#define TEGRA234_CLK_I2S6 66U146/** @brief clock recovered from I2S6 input */147#define TEGRA234_CLK_I2S6_SYNC_INPUT 67U148/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */149#define TEGRA234_CLK_ISP 69U150/** @brief Monitored branch of EQOS_RX clock */151#define TEGRA234_CLK_EQOS_RX_M 70U152/** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */153#define TEGRA234_CLK_MAUD 71U154/** @brief output of gate CLK_ENB_MIPI_CAL */155#define TEGRA234_CLK_MIPI_CAL 72U156/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */157#define TEGRA234_CLK_MPHY_CORE_PLL_FIXED 73U158/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */159#define TEGRA234_CLK_MPHY_L0_RX_ANA 74U160/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */161#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT 75U162/** @brief output of gate CLK_ENB_MPHY_L0_RX_SYMB */163#define TEGRA234_CLK_MPHY_L0_RX_SYMB 76U164/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */165#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT 77U166/** @brief output of gate CLK_ENB_MPHY_L0_TX_SYMB */167#define TEGRA234_CLK_MPHY_L0_TX_SYMB 78U168/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */169#define TEGRA234_CLK_MPHY_L1_RX_ANA 79U170/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */171#define TEGRA234_CLK_MPHY_TX_1MHZ_REF 80U172/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */173#define TEGRA234_CLK_NVCSI 81U174/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */175#define TEGRA234_CLK_NVCSILP 82U176/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */177#define TEGRA234_CLK_NVDEC 83U178/** @brief CLK_RST_CONTROLLER_HUBCLK_OUT_SWITCH_DIVIDER switch divider output (hubclk) */179#define TEGRA234_CLK_HUB 84U180/** @brief CLK_RST_CONTROLLER_DISPCLK_SWITCH_DIVIDER switch divider output (dispclk) */181#define TEGRA234_CLK_DISP 85U182/** @brief RG_CLK_CTRL__0_DIV divider output (nvdisplay_p0_clk) */183#define TEGRA234_CLK_NVDISPLAY_P0 86U184/** @brief RG_CLK_CTRL__1_DIV divider output (nvdisplay_p1_clk) */185#define TEGRA234_CLK_NVDISPLAY_P1 87U186/** @brief DSC_CLK (DISPCLK ÷ 3) */187#define TEGRA234_CLK_DSC 88U188/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */189#define TEGRA234_CLK_NVENC 89U190/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */191#define TEGRA234_CLK_NVJPG 90U192/** @brief input from Tegra's XTAL_IN */193#define TEGRA234_CLK_OSC 91U194/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH switch divider output */195#define TEGRA234_CLK_AON_TOUCH 92U196/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */197#define TEGRA234_CLK_PLLA 93U198/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */199#define TEGRA234_CLK_PLLAON 94U200/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */201#define TEGRA234_CLK_PLLE 100U202/** @brief PLLP vco output */203#define TEGRA234_CLK_PLLP 101U204/** @brief PLLP clk output */205#define TEGRA234_CLK_PLLP_OUT0 102U206/** Fixed frequency 960MHz PLL for USB and EAVB */207#define TEGRA234_CLK_UTMIP_PLL 103U208/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */209#define TEGRA234_CLK_PLLA_OUT0 104U210/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */211#define TEGRA234_CLK_PWM1 105U212/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */213#define TEGRA234_CLK_PWM2 106U214/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */215#define TEGRA234_CLK_PWM3 107U216/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */217#define TEGRA234_CLK_PWM4 108U218/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */219#define TEGRA234_CLK_PWM5 109U220/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */221#define TEGRA234_CLK_PWM6 110U222/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */223#define TEGRA234_CLK_PWM7 111U224/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */225#define TEGRA234_CLK_PWM8 112U226/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC output */227#define TEGRA234_CLK_RCE_CPU_NIC 113U228/** @brief CLK_RST_CONTROLLER_RCE_NIC_RATE divider output */229#define TEGRA234_CLK_RCE_NIC 114U230/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW switch divider output */231#define TEGRA234_CLK_AON_I2C_SLOW 117U232/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */233#define TEGRA234_CLK_SCE_CPU_NIC 118U234/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */235#define TEGRA234_CLK_SCE_NIC 119U236/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */237#define TEGRA234_CLK_SDMMC1 120U238/** @brief Logical clk for setting the UPHY PLL3 rate */239#define TEGRA234_CLK_UPHY_PLL3 121U240/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */241#define TEGRA234_CLK_SDMMC4 123U242/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */243#define TEGRA234_CLK_SE 124U244/** @brief VPLL select for sor0_ref clk driven by disp_2clk_sor0_head_sel signal */245#define TEGRA234_CLK_SOR0_PLL_REF 125U246/** @brief Output of mux controlled by disp_2clk_sor0_pll_ref_clk_safe signal (sor0_ref_clk) */247#define TEGRA234_CLK_SOR0_REF 126U248/** @brief VPLL select for sor1_ref clk driven by disp_2clk_sor0_head_sel signal */249#define TEGRA234_CLK_SOR1_PLL_REF 127U250/** @brief SOR_PLL_REF_CLK_CTRL__0_DIV divider output */251#define TEGRA234_CLK_PRE_SOR0_REF 128U252/** @brief Output of mux controlled by disp_2clk_sor1_pll_ref_clk_safe signal (sor1_ref_clk) */253#define TEGRA234_CLK_SOR1_REF 129U254/** @brief SOR_PLL_REF_CLK_CTRL__1_DIV divider output */255#define TEGRA234_CLK_PRE_SOR1_REF 130U256/** @brief output of gate CLK_ENB_SOR_SAFE */257#define TEGRA234_CLK_SOR_SAFE 131U258/** @brief SOR_CLK_CTRL__0_DIV divider output */259#define TEGRA234_CLK_SOR0_DIV 132U260/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */261#define TEGRA234_CLK_DMIC5 134U262/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */263#define TEGRA234_CLK_SPI1 135U264/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */265#define TEGRA234_CLK_SPI2 136U266/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI3 */267#define TEGRA234_CLK_SPI3 137U268/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */269#define TEGRA234_CLK_I2C_SLOW 138U270/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */271#define TEGRA234_CLK_SYNC_DMIC1 139U272/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */273#define TEGRA234_CLK_SYNC_DMIC2 140U274/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */275#define TEGRA234_CLK_SYNC_DMIC3 141U276/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */277#define TEGRA234_CLK_SYNC_DMIC4 142U278/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */279#define TEGRA234_CLK_SYNC_DSPK1 143U280/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */281#define TEGRA234_CLK_SYNC_DSPK2 144U282/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */283#define TEGRA234_CLK_SYNC_I2S1 145U284/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */285#define TEGRA234_CLK_SYNC_I2S2 146U286/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */287#define TEGRA234_CLK_SYNC_I2S3 147U288/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */289#define TEGRA234_CLK_SYNC_I2S4 148U290/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */291#define TEGRA234_CLK_SYNC_I2S5 149U292/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */293#define TEGRA234_CLK_SYNC_I2S6 150U294/** @brief controls MPHY_FORCE_LS_MODE upon enable & disable */295#define TEGRA234_CLK_MPHY_FORCE_LS_MODE 151U296/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH0 */297#define TEGRA234_CLK_TACH0 152U298/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */299#define TEGRA234_CLK_TSEC 153U300/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */301#define TEGRA234_CLK_TSEC_PKA 154U302/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */303#define TEGRA234_CLK_UARTA 155U304/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */305#define TEGRA234_CLK_UARTB 156U306/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */307#define TEGRA234_CLK_UARTC 157U308/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */309#define TEGRA234_CLK_UARTD 158U310/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */311#define TEGRA234_CLK_UARTE 159U312/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */313#define TEGRA234_CLK_UARTF 160U314/** @brief output of gate CLK_ENB_PEX1_CORE_6 */315#define TEGRA234_CLK_PEX1_C6_CORE 161U316/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */317#define TEGRA234_CLK_UART_FST_MIPI_CAL 162U318/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */319#define TEGRA234_CLK_UFSDEV_REF 163U320/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */321#define TEGRA234_CLK_UFSHC 164U322/** @brief output of gate CLK_ENB_USB2_TRK */323#define TEGRA234_CLK_USB2_TRK 165U324/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */325#define TEGRA234_CLK_VI 166U326/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */327#define TEGRA234_CLK_VIC 167U328/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_CSITE switch divider output */329#define TEGRA234_CLK_CSITE 168U330/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_IST switch divider output */331#define TEGRA234_CLK_IST 169U332/** @brief output of mux controlled by CLK_RST_CONTROLLER_IST_JTAG_REG_CLK_SEL */333#define TEGRA234_CLK_JTAG_INTFC_PRE_CG 170U334/** @brief output of gate CLK_ENB_PEX2_CORE_7 */335#define TEGRA234_CLK_PEX2_C7_CORE 171U336/** @brief output of gate CLK_ENB_PEX2_CORE_8 */337#define TEGRA234_CLK_PEX2_C8_CORE 172U338/** @brief output of gate CLK_ENB_PEX2_CORE_9 */339#define TEGRA234_CLK_PEX2_C9_CORE 173U340/** @brief dla0_falcon_clk */341#define TEGRA234_CLK_DLA0_FALCON 174U342/** @brief dla0_core_clk */343#define TEGRA234_CLK_DLA0_CORE 175U344/** @brief dla1_falcon_clk */345#define TEGRA234_CLK_DLA1_FALCON 176U346/** @brief dla1_core_clk */347#define TEGRA234_CLK_DLA1_CORE 177U348/** @brief Output of mux controlled by disp_2clk_sor0_clk_safe signal (sor0_clk) */349#define TEGRA234_CLK_SOR0 178U350/** @brief Output of mux controlled by disp_2clk_sor1_clk_safe signal (sor1_clk) */351#define TEGRA234_CLK_SOR1 179U352/** @brief DP macro feedback clock (same as LINKA_SYM CLKOUT) */353#define TEGRA234_CLK_SOR_PAD_INPUT 180U354/** @brief Output of mux controlled by disp_2clk_h0_dsi_sel signal in sf0_clk path */355#define TEGRA234_CLK_PRE_SF0 181U356/** @brief Output of mux controlled by disp_2clk_sf0_clk_safe signal (sf0_clk) */357#define TEGRA234_CLK_SF0 182U358/** @brief Output of mux controlled by disp_2clk_sf1_clk_safe signal (sf1_clk) */359#define TEGRA234_CLK_SF1 183U360/** @brief CLKOUT_AB output from DSI BRICK A (dsi_clkout_ab) */361#define TEGRA234_CLK_DSI_PAD_INPUT 184U362/** @brief output of gate CLK_ENB_PEX2_CORE_10 */363#define TEGRA234_CLK_PEX2_C10_CORE 187U364/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTI switch divider output (uarti_r_clk) */365#define TEGRA234_CLK_UARTI 188U366/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ switch divider output (uartj_r_clk) */367#define TEGRA234_CLK_UARTJ 189U368/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH switch divider output */369#define TEGRA234_CLK_UARTH 190U370/** @brief ungated version of fuse clk */371#define TEGRA234_CLK_FUSE_SERIAL 191U372/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output (qspi0_2x_pm_clk) */373#define TEGRA234_CLK_QSPI0_2X_PM 192U374/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output (qspi1_2x_pm_clk) */375#define TEGRA234_CLK_QSPI1_2X_PM 193U376/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 (qspi0_pm_clk) */377#define TEGRA234_CLK_QSPI0_PM 194U378/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 (qspi1_pm_clk) */379#define TEGRA234_CLK_QSPI1_PM 195U380/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST switch divider output */381#define TEGRA234_CLK_VI_CONST 196U382/** @brief NAFLL clock source for BPMP */383#define TEGRA234_CLK_NAFLL_BPMP 197U384/** @brief NAFLL clock source for SCE */385#define TEGRA234_CLK_NAFLL_SCE 198U386/** @brief NAFLL clock source for NVDEC */387#define TEGRA234_CLK_NAFLL_NVDEC 199U388/** @brief NAFLL clock source for NVJPG */389#define TEGRA234_CLK_NAFLL_NVJPG 200U390/** @brief NAFLL clock source for TSEC */391#define TEGRA234_CLK_NAFLL_TSEC 201U392/** @brief NAFLL clock source for VI */393#define TEGRA234_CLK_NAFLL_VI 203U394/** @brief NAFLL clock source for SE */395#define TEGRA234_CLK_NAFLL_SE 204U396/** @brief NAFLL clock source for NVENC */397#define TEGRA234_CLK_NAFLL_NVENC 205U398/** @brief NAFLL clock source for ISP */399#define TEGRA234_CLK_NAFLL_ISP 206U400/** @brief NAFLL clock source for VIC */401#define TEGRA234_CLK_NAFLL_VIC 207U402/** @brief NAFLL clock source for AXICBB */403#define TEGRA234_CLK_NAFLL_AXICBB 209U404/** @brief NAFLL clock source for NVJPG1 */405#define TEGRA234_CLK_NAFLL_NVJPG1 210U406/** @brief NAFLL clock source for PVA core */407#define TEGRA234_CLK_NAFLL_PVA0_CORE 211U408/** @brief NAFLL clock source for PVA VPS */409#define TEGRA234_CLK_NAFLL_PVA0_VPS 212U410/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0 switch divider output (dbgapb_clk) */411#define TEGRA234_CLK_DBGAPB 213U412/** @brief NAFLL clock source for RCE */413#define TEGRA234_CLK_NAFLL_RCE 214U414/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_LA switch divider output (la_r_clk) */415#define TEGRA234_CLK_LA 215U416/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTD */417#define TEGRA234_CLK_PLLP_OUT_JTAG 216U418/** @brief AXI_CBB branch sharing gate control with SDMMC4 */419#define TEGRA234_CLK_SDMMC4_AXICIF 217U420/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */421#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U422/** @brief output of gate CLK_ENB_PEX0_CORE_0 */423#define TEGRA234_CLK_PEX0_C0_CORE 220U424/** @brief output of gate CLK_ENB_PEX0_CORE_1 */425#define TEGRA234_CLK_PEX0_C1_CORE 221U426/** @brief output of gate CLK_ENB_PEX0_CORE_2 */427#define TEGRA234_CLK_PEX0_C2_CORE 222U428/** @brief output of gate CLK_ENB_PEX0_CORE_3 */429#define TEGRA234_CLK_PEX0_C3_CORE 223U430/** @brief output of gate CLK_ENB_PEX0_CORE_4 */431#define TEGRA234_CLK_PEX0_C4_CORE 224U432/** @brief output of gate CLK_ENB_PEX1_CORE_5 */433#define TEGRA234_CLK_PEX1_C5_CORE 225U434/** @brief Monitored branch of PEX0_C0_CORE clock */435#define TEGRA234_CLK_PEX0_C0_CORE_M 229U436/** @brief Monitored branch of PEX0_C1_CORE clock */437#define TEGRA234_CLK_PEX0_C1_CORE_M 230U438/** @brief Monitored branch of PEX0_C2_CORE clock */439#define TEGRA234_CLK_PEX0_C2_CORE_M 231U440/** @brief Monitored branch of PEX0_C3_CORE clock */441#define TEGRA234_CLK_PEX0_C3_CORE_M 232U442/** @brief Monitored branch of PEX0_C4_CORE clock */443#define TEGRA234_CLK_PEX0_C4_CORE_M 233U444/** @brief Monitored branch of PEX1_C5_CORE clock */445#define TEGRA234_CLK_PEX1_C5_CORE_M 234U446/** @brief Monitored branch of PEX1_C6_CORE clock */447#define TEGRA234_CLK_PEX1_C6_CORE_M 235U448/** @brief output of GPU GPC1 clkGen (in 1x mode same rate as GPC1 MUX2 out) */449#define TEGRA234_CLK_GPC1CLK 236U450/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */451#define TEGRA234_CLK_PLLC4 237U452/** @brief PLLC4 VCO followed by DIV3 path */453#define TEGRA234_CLK_PLLC4_OUT1 239U454/** @brief PLLC4 VCO followed by DIV5 path */455#define TEGRA234_CLK_PLLC4_OUT2 240U456/** @brief output of the mux controlled by PLLC4_CLK_SEL */457#define TEGRA234_CLK_PLLC4_MUXED 241U458/** @brief PLLC4 VCO followed by DIV2 path */459#define TEGRA234_CLK_PLLC4_VCO_DIV2 242U460/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVHS_BASE */461#define TEGRA234_CLK_PLLNVHS 243U462/** @brief Monitored branch of PEX2_C7_CORE clock */463#define TEGRA234_CLK_PEX2_C7_CORE_M 244U464/** @brief Monitored branch of PEX2_C8_CORE clock */465#define TEGRA234_CLK_PEX2_C8_CORE_M 245U466/** @brief Monitored branch of PEX2_C9_CORE clock */467#define TEGRA234_CLK_PEX2_C9_CORE_M 246U468/** @brief Monitored branch of PEX2_C10_CORE clock */469#define TEGRA234_CLK_PEX2_C10_CORE_M 247U470/** @brief RX clock recovered from MGBE0 lane input */471#define TEGRA234_CLK_MGBE0_RX_INPUT 248U472/** @brief RX clock recovered from MGBE1 lane input */473#define TEGRA234_CLK_MGBE1_RX_INPUT 249U474/** @brief RX clock recovered from MGBE2 lane input */475#define TEGRA234_CLK_MGBE2_RX_INPUT 250U476/** @brief RX clock recovered from MGBE3 lane input */477#define TEGRA234_CLK_MGBE3_RX_INPUT 251U478/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP switch divider output */479#define TEGRA234_CLK_PEX_SATA_USB_RX_BYP 254U480/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT switch divider output */481#define TEGRA234_CLK_PEX_USB_PAD_PLL0_MGMT 255U482/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT switch divider output */483#define TEGRA234_CLK_PEX_USB_PAD_PLL1_MGMT 256U484/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT switch divider output */485#define TEGRA234_CLK_PEX_USB_PAD_PLL2_MGMT 257U486/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT switch divider output */487#define TEGRA234_CLK_PEX_USB_PAD_PLL3_MGMT 258U488/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP switch divider output */489#define TEGRA234_CLK_NVHS_RX_BYP_REF 263U490/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT switch divider output */491#define TEGRA234_CLK_NVHS_PLL0_MGMT 264U492/** @brief xusb_core_dev_clk */493#define TEGRA234_CLK_XUSB_CORE_DEV 265U494/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST switch divider output */495#define TEGRA234_CLK_XUSB_CORE_MUX 266U496/** @brief xusb_core_host_clk */497#define TEGRA234_CLK_XUSB_CORE_HOST 267U498/** @brief xusb_core_superspeed_clk */499#define TEGRA234_CLK_XUSB_CORE_SS 268U500/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON switch divider output */501#define TEGRA234_CLK_XUSB_FALCON 269U502/** @brief xusb_falcon_host_clk */503#define TEGRA234_CLK_XUSB_FALCON_HOST 270U504/** @brief xusb_falcon_superspeed_clk */505#define TEGRA234_CLK_XUSB_FALCON_SS 271U506/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS switch divider output */507#define TEGRA234_CLK_XUSB_FS 272U508/** @brief xusb_fs_host_clk */509#define TEGRA234_CLK_XUSB_FS_HOST 273U510/** @brief xusb_fs_dev_clk */511#define TEGRA234_CLK_XUSB_FS_DEV 274U512/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS switch divider output */513#define TEGRA234_CLK_XUSB_SS 275U514/** @brief xusb_ss_dev_clk */515#define TEGRA234_CLK_XUSB_SS_DEV 276U516/** @brief xusb_ss_superspeed_clk */517#define TEGRA234_CLK_XUSB_SS_SUPERSPEED 277U518/** @brief NAFLL clock source for CPU cluster 0 */519#define TEGRA234_CLK_NAFLL_CLUSTER0 280U /* TODO: remove */520#define TEGRA234_CLK_NAFLL_CLUSTER0_CORE 280U521/** @brief NAFLL clock source for CPU cluster 1 */522#define TEGRA234_CLK_NAFLL_CLUSTER1 281U /* TODO: remove */523#define TEGRA234_CLK_NAFLL_CLUSTER1_CORE 281U524/** @brief NAFLL clock source for CPU cluster 2 */525#define TEGRA234_CLK_NAFLL_CLUSTER2 282U /* TODO: remove */526#define TEGRA234_CLK_NAFLL_CLUSTER2_CORE 282U527/** @brief CLK_RST_CONTROLLER_CAN1_CORE_RATE divider output */528#define TEGRA234_CLK_CAN1_CORE 284U529/** @brief CLK_RST_CONTROLLER_CAN2_CORE_RATE divider outputt */530#define TEGRA234_CLK_CAN2_CORE 285U531/** @brief CLK_RST_CONTROLLER_PLLA1_OUT1 switch divider output */532#define TEGRA234_CLK_PLLA1_OUT1 286U533/** @brief NVHS PLL hardware power sequencer (overrides 'manual' programming of PLL) */534#define TEGRA234_CLK_PLLNVHS_HPS 287U535/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE */536#define TEGRA234_CLK_PLLREFE_VCOOUT 288U537/** @brief 32K input clock provided by PMIC */538#define TEGRA234_CLK_CLK_32K 289U539/** @brief Fixed 48MHz clock divided down from utmipll */540#define TEGRA234_CLK_UTMIPLL_CLKOUT48 291U541/** @brief Fixed 480MHz clock divided down from utmipll */542#define TEGRA234_CLK_UTMIPLL_CLKOUT480 292U543/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */544#define TEGRA234_CLK_PLLNVCSI 294U545/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI switch divider output */546#define TEGRA234_CLK_PVA0_CPU_AXI 295U547/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS switch divider output */548#define TEGRA234_CLK_PVA0_VPS 297U549/** @brief DLA0_CORE_NAFLL */550#define TEGRA234_CLK_NAFLL_DLA0_CORE 299U551/** @brief DLA0_FALCON_NAFLL */552#define TEGRA234_CLK_NAFLL_DLA0_FALCON 300U553/** @brief DLA1_CORE_NAFLL */554#define TEGRA234_CLK_NAFLL_DLA1_CORE 301U555/** @brief DLA1_FALCON_NAFLL */556#define TEGRA234_CLK_NAFLL_DLA1_FALCON 302U557/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */558#define TEGRA234_CLK_AON_UART_FST_MIPI_CAL 303U559/** @brief GPU system clock */560#define TEGRA234_CLK_GPUSYS 304U561/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 */562#define TEGRA234_CLK_I2C5 305U563/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider free running clk */564#define TEGRA234_CLK_FR_SE 306U565/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC switch divider output */566#define TEGRA234_CLK_BPMP_CPU_NIC 307U567/** @brief output of gate CLK_ENB_BPMP_CPU */568#define TEGRA234_CLK_BPMP_CPU 308U569/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSC switch divider output */570#define TEGRA234_CLK_TSC 309U571/** @brief output of mem pll A sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMC */572#define TEGRA234_CLK_EMCSA_MPLL 310U573/** @brief output of mem pll B sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB */574#define TEGRA234_CLK_EMCSB_MPLL 311U575/** @brief output of mem pll C sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC */576#define TEGRA234_CLK_EMCSC_MPLL 312U577/** @brief output of mem pll D sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD */578#define TEGRA234_CLK_EMCSD_MPLL 313U579/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */580#define TEGRA234_CLK_PLLC 314U581/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */582#define TEGRA234_CLK_PLLC2 315U583/** @brief CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER skip divider output */584#define TEGRA234_CLK_TSC_REF 317U585/** @brief Dummy clock to ensure minimum SoC voltage for fuse burning */586#define TEGRA234_CLK_FUSE_BURN 318U587/** @brief GBE PLL */588#define TEGRA234_CLK_PLLGBE 319U589/** @brief GBE PLL hardware power sequencer */590#define TEGRA234_CLK_PLLGBE_HPS 320U591/** @brief output of EMC CDB side A fixed (DIV4) divider */592#define TEGRA234_CLK_EMCSA_EMC 321U593/** @brief output of EMC CDB side B fixed (DIV4) divider */594#define TEGRA234_CLK_EMCSB_EMC 322U595/** @brief output of EMC CDB side C fixed (DIV4) divider */596#define TEGRA234_CLK_EMCSC_EMC 323U597/** @brief output of EMC CDB side D fixed (DIV4) divider */598#define TEGRA234_CLK_EMCSD_EMC 324U599/** @brief PLLE hardware power sequencer (overrides 'manual' programming of PLL) */600#define TEGRA234_CLK_PLLE_HPS 326U601/** @brief CLK_ENB_PLLREFE_OUT gate output */602#define TEGRA234_CLK_PLLREFE_VCOOUT_GATED 327U603/** @brief TEGRA234_CLK_SOR_SAFE clk source (PLLP_OUT0 divided by 17) */604#define TEGRA234_CLK_PLLP_DIV17 328U605/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM switch divider output */606#define TEGRA234_CLK_SOC_THERM 329U607/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSENSE switch divider output */608#define TEGRA234_CLK_TSENSE 330U609/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider free running clk */610#define TEGRA234_CLK_FR_SEU1 331U611/** @brief NAFLL clock source for OFA */612#define TEGRA234_CLK_NAFLL_OFA 333U613/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_OFA switch divider output */614#define TEGRA234_CLK_OFA 334U615/** @brief NAFLL clock source for SEU1 */616#define TEGRA234_CLK_NAFLL_SEU1 335U617/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider gated output */618#define TEGRA234_CLK_SEU1 336U619/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */620#define TEGRA234_CLK_SPI4 337U621/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI5 */622#define TEGRA234_CLK_SPI5 338U623/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DCE_CPU_NIC */624#define TEGRA234_CLK_DCE_CPU_NIC 339U625/** @brief output of divider CLK_RST_CONTROLLER_DCE_NIC_RATE */626#define TEGRA234_CLK_DCE_NIC 340U627/** @brief NAFLL clock source for DCE */628#define TEGRA234_CLK_NAFLL_DCE 341U629/** @brief Monitored branch of MPHY_L0_RX_ANA clock */630#define TEGRA234_CLK_MPHY_L0_RX_ANA_M 342U631/** @brief Monitored branch of MPHY_L1_RX_ANA clock */632#define TEGRA234_CLK_MPHY_L1_RX_ANA_M 343U633/** @brief ungated version of TX symbol clock after fixed 1/2 divider */634#define TEGRA234_CLK_MPHY_L0_TX_PRE_SYMB 344U635/** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */636#define TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV 345U637/** @brief output of gate CLK_ENB_MPHY_L0_TX_2X_SYMB */638#define TEGRA234_CLK_MPHY_L0_TX_2X_SYMB 346U639/** @brief output of SW_MPHY_L0_TX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */640#define TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV 347U641/** @brief output of SW_MPHY_L0_TX_LS_3XBIT divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */642#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV 348U643/** @brief LS/HS divider mux SW_MPHY_L0_TX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */644#define TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV 349U645/** @brief Monitored branch of MPHY_L0_TX_SYMB clock */646#define TEGRA234_CLK_MPHY_L0_TX_SYMB_M 350U647/** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */648#define TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV 351U649/** @brief output of SW_MPHY_L0_RX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */650#define TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV 352U651/** @brief output of SW_MPHY_L0_RX_LS_BIT divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */652#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV 353U653/** @brief LS/HS divider mux SW_MPHY_L0_RX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */654#define TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV 354U655/** @brief Monitored branch of MPHY_L0_RX_SYMB clock */656#define TEGRA234_CLK_MPHY_L0_RX_SYMB_M 355U657/** @brief Monitored branch of MBGE0 RX input clock */658#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U659/** @brief Monitored branch of MBGE1 RX input clock */660#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U661/** @brief Monitored branch of MBGE2 RX input clock */662#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U663/** @brief Monitored branch of MBGE3 RX input clock */664#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U665/** @brief Monitored branch of MGBE0 RX PCS mux output */666#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U667/** @brief Monitored branch of MGBE1 RX PCS mux output */668#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U669/** @brief Monitored branch of MGBE2 RX PCS mux output */670#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U671/** @brief Monitored branch of MGBE3 RX PCS mux output */672#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U673/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH1 */674#define TEGRA234_CLK_TACH1 365U675/** @brief GBE_UPHY_MGBES_APP_CLK switch divider gated output */676#define TEGRA234_CLK_MGBES_APP 366U677/** @brief Logical clk for setting GBE UPHY PLL2 TX_REF rate */678#define TEGRA234_CLK_UPHY_GBE_PLL2_TX_REF 367U679/** @brief Logical clk for setting GBE UPHY PLL2 XDIG rate */680#define TEGRA234_CLK_UPHY_GBE_PLL2_XDIG 368U681/** @brief RX PCS clock recovered from MGBE0 lane input */682#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U683/** @brief RX PCS clock recovered from MGBE1 lane input */684#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U685/** @brief RX PCS clock recovered from MGBE2 lane input */686#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U687/** @brief RX PCS clock recovered from MGBE3 lane input */688#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U689/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */690#define TEGRA234_CLK_MGBE0_RX_PCS 373U691/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */692#define TEGRA234_CLK_MGBE0_TX 374U693/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */694#define TEGRA234_CLK_MGBE0_TX_PCS 375U695/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */696#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U697/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */698#define TEGRA234_CLK_MGBE0_MAC 377U699/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */700#define TEGRA234_CLK_MGBE0_MACSEC 378U701/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */702#define TEGRA234_CLK_MGBE0_EEE_PCS 379U703/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */704#define TEGRA234_CLK_MGBE0_APP 380U705/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */706#define TEGRA234_CLK_MGBE0_PTP_REF 381U707/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */708#define TEGRA234_CLK_MGBE1_RX_PCS 382U709/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */710#define TEGRA234_CLK_MGBE1_TX 383U711/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */712#define TEGRA234_CLK_MGBE1_TX_PCS 384U713/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */714#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U715/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */716#define TEGRA234_CLK_MGBE1_MAC 386U717/** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate output */718#define TEGRA234_CLK_MGBE1_MACSEC 387U719/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */720#define TEGRA234_CLK_MGBE1_EEE_PCS 388U721/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */722#define TEGRA234_CLK_MGBE1_APP 389U723/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */724#define TEGRA234_CLK_MGBE1_PTP_REF 390U725/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */726#define TEGRA234_CLK_MGBE2_RX_PCS 391U727/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */728#define TEGRA234_CLK_MGBE2_TX 392U729/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */730#define TEGRA234_CLK_MGBE2_TX_PCS 393U731/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */732#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U733/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */734#define TEGRA234_CLK_MGBE2_MAC 395U735/** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate output */736#define TEGRA234_CLK_MGBE2_MACSEC 396U737/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */738#define TEGRA234_CLK_MGBE2_EEE_PCS 397U739/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */740#define TEGRA234_CLK_MGBE2_APP 398U741/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */742#define TEGRA234_CLK_MGBE2_PTP_REF 399U743/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */744#define TEGRA234_CLK_MGBE3_RX_PCS 400U745/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */746#define TEGRA234_CLK_MGBE3_TX 401U747/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */748#define TEGRA234_CLK_MGBE3_TX_PCS 402U749/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */750#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U751/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */752#define TEGRA234_CLK_MGBE3_MAC 404U753/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */754#define TEGRA234_CLK_MGBE3_MACSEC 405U755/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */756#define TEGRA234_CLK_MGBE3_EEE_PCS 406U757/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */758#define TEGRA234_CLK_MGBE3_APP 407U759/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */760#define TEGRA234_CLK_MGBE3_PTP_REF 408U761/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_RX_BYP switch divider output */762#define TEGRA234_CLK_GBE_RX_BYP_REF 409U763/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL0_MGMT switch divider output */764#define TEGRA234_CLK_GBE_PLL0_MGMT 410U765/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL1_MGMT switch divider output */766#define TEGRA234_CLK_GBE_PLL1_MGMT 411U767/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL2_MGMT switch divider output */768#define TEGRA234_CLK_GBE_PLL2_MGMT 412U769/** @brief output of gate CLK_ENB_EQOS_MACSEC_RX */770#define TEGRA234_CLK_EQOS_MACSEC_RX 413U771/** @brief output of gate CLK_ENB_EQOS_MACSEC_TX */772#define TEGRA234_CLK_EQOS_MACSEC_TX 414U773/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider ungated output */774#define TEGRA234_CLK_EQOS_TX_DIVIDER 415U775/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL1_MGMT switch divider output */776#define TEGRA234_CLK_NVHS_PLL1_MGMT 416U777/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EMCHUB mux output */778#define TEGRA234_CLK_EMCHUB 417U779/** @brief clock recovered from I2S7 input */780#define TEGRA234_CLK_I2S7_SYNC_INPUT 418U781/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S7 */782#define TEGRA234_CLK_SYNC_I2S7 419U783/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S7 */784#define TEGRA234_CLK_I2S7 420U785/** @brief Monitored output of I2S7 pad macro mux */786#define TEGRA234_CLK_I2S7_PAD_M 421U787/** @brief clock recovered from I2S8 input */788#define TEGRA234_CLK_I2S8_SYNC_INPUT 422U789/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S8 */790#define TEGRA234_CLK_SYNC_I2S8 423U791/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S8 */792#define TEGRA234_CLK_I2S8 424U793/** @brief Monitored output of I2S8 pad macro mux */794#define TEGRA234_CLK_I2S8_PAD_M 425U795/** @brief NAFLL clock source for GPU GPC0 */796#define TEGRA234_CLK_NAFLL_GPC0 426U797/** @brief NAFLL clock source for GPU GPC1 */798#define TEGRA234_CLK_NAFLL_GPC1 427U799/** @brief NAFLL clock source for GPU SYSCLK */800#define TEGRA234_CLK_NAFLL_GPUSYS 428U801/** @brief NAFLL clock source for CPU cluster 0 DSUCLK */802#define TEGRA234_CLK_NAFLL_DSU0 429U /* TODO: remove */803#define TEGRA234_CLK_NAFLL_CLUSTER0_DSU 429U804/** @brief NAFLL clock source for CPU cluster 1 DSUCLK */805#define TEGRA234_CLK_NAFLL_DSU1 430U /* TODO: remove */806#define TEGRA234_CLK_NAFLL_CLUSTER1_DSU 430U807/** @brief NAFLL clock source for CPU cluster 2 DSUCLK */808#define TEGRA234_CLK_NAFLL_DSU2 431U /* TODO: remove */809#define TEGRA234_CLK_NAFLL_CLUSTER2_DSU 431U810/** @brief output of gate CLK_ENB_SCE_CPU */811#define TEGRA234_CLK_SCE_CPU 432U812/** @brief output of gate CLK_ENB_RCE_CPU */813#define TEGRA234_CLK_RCE_CPU 433U814/** @brief output of gate CLK_ENB_DCE_CPU */815#define TEGRA234_CLK_DCE_CPU 434U816/** @brief DSIPLL VCO output */817#define TEGRA234_CLK_DSIPLL_VCO 435U818/** @brief DSIPLL SYNC_CLKOUTP/N differential output */819#define TEGRA234_CLK_DSIPLL_CLKOUTPN 436U820/** @brief DSIPLL SYNC_CLKOUTA output */821#define TEGRA234_CLK_DSIPLL_CLKOUTA 437U822/** @brief SPPLL0 VCO output */823#define TEGRA234_CLK_SPPLL0_VCO 438U824/** @brief SPPLL0 SYNC_CLKOUTP/N differential output */825#define TEGRA234_CLK_SPPLL0_CLKOUTPN 439U826/** @brief SPPLL0 SYNC_CLKOUTA output */827#define TEGRA234_CLK_SPPLL0_CLKOUTA 440U828/** @brief SPPLL0 SYNC_CLKOUTB output */829#define TEGRA234_CLK_SPPLL0_CLKOUTB 441U830/** @brief SPPLL0 CLKOUT_DIVBY10 output */831#define TEGRA234_CLK_SPPLL0_DIV10 442U832/** @brief SPPLL0 CLKOUT_DIVBY25 output */833#define TEGRA234_CLK_SPPLL0_DIV25 443U834/** @brief SPPLL0 CLKOUT_DIVBY27P/N differential output */835#define TEGRA234_CLK_SPPLL0_DIV27PN 444U836/** @brief SPPLL1 VCO output */837#define TEGRA234_CLK_SPPLL1_VCO 445U838/** @brief SPPLL1 SYNC_CLKOUTP/N differential output */839#define TEGRA234_CLK_SPPLL1_CLKOUTPN 446U840/** @brief SPPLL1 CLKOUT_DIVBY27P/N differential output */841#define TEGRA234_CLK_SPPLL1_DIV27PN 447U842/** @brief VPLL0 reference clock */843#define TEGRA234_CLK_VPLL0_REF 448U844/** @brief VPLL0 */845#define TEGRA234_CLK_VPLL0 449U846/** @brief VPLL1 */847#define TEGRA234_CLK_VPLL1 450U848/** @brief NVDISPLAY_P0_CLK reference select */849#define TEGRA234_CLK_NVDISPLAY_P0_REF 451U850/** @brief RG0_PCLK */851#define TEGRA234_CLK_RG0 452U852/** @brief RG1_PCLK */853#define TEGRA234_CLK_RG1 453U854/** @brief DISPPLL output */855#define TEGRA234_CLK_DISPPLL 454U856/** @brief DISPHUBPLL output */857#define TEGRA234_CLK_DISPHUBPLL 455U858/** @brief CLK_RST_CONTROLLER_DSI_LP_SWITCH_DIVIDER switch divider output (dsi_lp_clk) */859#define TEGRA234_CLK_DSI_LP 456U860/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */861#define TEGRA234_CLK_AZA_2XBIT 457U862/** @brief aza_2xbitclk / 2 (aza_bitclk) */863#define TEGRA234_CLK_AZA_BIT 458U864/** @brief SWITCH_DSI_CORE_PIXEL_MISC_DSI_CORE_CLK_SRC switch output (dsi_core_clk) */865#define TEGRA234_CLK_DSI_CORE 459U866/** @brief Output of mux controlled by pkt_wr_fifo_signal from dsi (dsi_pixel_clk) */867#define TEGRA234_CLK_DSI_PIXEL 460U868/** @brief Output of mux controlled by disp_2clk_sor0_dp_sel (pre_sor0_clk) */869#define TEGRA234_CLK_PRE_SOR0 461U870/** @brief Output of mux controlled by disp_2clk_sor1_dp_sel (pre_sor1_clk) */871#define TEGRA234_CLK_PRE_SOR1 462U872/** @brief CLK_RST_CONTROLLER_LINK_REFCLK_CFG__0 output */873#define TEGRA234_CLK_DP_LINK_REF 463U874/** @brief Link clock input from DP macro brick PLL */875#define TEGRA234_CLK_SOR_LINKA_INPUT 464U876/** @brief SOR AFIFO clock outut */877#define TEGRA234_CLK_SOR_LINKA_AFIFO 465U878/** @brief Monitored branch of linka_afifo_clk */879#define TEGRA234_CLK_SOR_LINKA_AFIFO_M 466U880/** @brief Monitored branch of rg0_pclk */881#define TEGRA234_CLK_RG0_M 467U882/** @brief Monitored branch of rg1_pclk */883#define TEGRA234_CLK_RG1_M 468U884/** @brief Monitored branch of sor0_clk */885#define TEGRA234_CLK_SOR0_M 469U886/** @brief Monitored branch of sor1_clk */887#define TEGRA234_CLK_SOR1_M 470U888/** @brief EMC PLLHUB output */889#define TEGRA234_CLK_PLLHUB 471U890/** @brief output of fixed (DIV2) MC HUB divider */891#define TEGRA234_CLK_MCHUB 472U892/** @brief output of divider controlled by EMC side A MC_EMC_SAFE_SAME_FREQ */893#define TEGRA234_CLK_EMCSA_MC 473U894/** @brief output of divider controlled by EMC side B MC_EMC_SAFE_SAME_FREQ */895#define TEGRA234_CLK_EMCSB_MC 474U896/** @brief output of divider controlled by EMC side C MC_EMC_SAFE_SAME_FREQ */897#define TEGRA234_CLK_EMCSC_MC 475U898/** @brief output of divider controlled by EMC side D MC_EMC_SAFE_SAME_FREQ */899#define TEGRA234_CLK_EMCSD_MC 476U900 901/** @} */902 903#endif904