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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This header provides constants for binding nvidia,tegra30-car.4 *5 * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB6 * registers. These IDs often match those in the CAR's RST_DEVICES registers,7 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In8 * this case, those clocks are assigned IDs above 160 in order to highlight9 * this issue. Implementations that interpret these clock IDs as bit values10 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to11 * explicitly handle these special cases.12 *13 * The balance of the clocks controlled by the CAR are assigned IDs of 160 and14 * above.15 */16 17#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H18#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H19 20#define TEGRA30_CLK_CPU 021/* 1 */22/* 2 */23/* 3 */24#define TEGRA30_CLK_RTC 425#define TEGRA30_CLK_TIMER 526#define TEGRA30_CLK_UARTA 627/* 7 (register bit affects uartb and vfir) */28#define TEGRA30_CLK_GPIO 829#define TEGRA30_CLK_SDMMC2 930/* 10 (register bit affects spdif_in and spdif_out) */31#define TEGRA30_CLK_I2S1 1132#define TEGRA30_CLK_I2C1 1233#define TEGRA30_CLK_NDFLASH 1334#define TEGRA30_CLK_SDMMC1 1435#define TEGRA30_CLK_SDMMC4 1536/* 16 */37#define TEGRA30_CLK_PWM 1738#define TEGRA30_CLK_I2S2 1839#define TEGRA30_CLK_EPP 1940/* 20 (register bit affects vi and vi_sensor) */41#define TEGRA30_CLK_GR2D 2142#define TEGRA30_CLK_USBD 2243#define TEGRA30_CLK_ISP 2344#define TEGRA30_CLK_GR3D 2445/* 25 */46#define TEGRA30_CLK_DISP2 2647#define TEGRA30_CLK_DISP1 2748#define TEGRA30_CLK_HOST1X 2849#define TEGRA30_CLK_VCP 2950#define TEGRA30_CLK_I2S0 3051#define TEGRA30_CLK_COP_CACHE 3152 53#define TEGRA30_CLK_MC 3254#define TEGRA30_CLK_AHBDMA 3355#define TEGRA30_CLK_APBDMA 3456/* 35 */57#define TEGRA30_CLK_KBC 3658#define TEGRA30_CLK_STATMON 3759#define TEGRA30_CLK_PMC 3860/* 39 (register bit affects fuse and fuse_burn) */61#define TEGRA30_CLK_KFUSE 4062#define TEGRA30_CLK_SBC1 4163#define TEGRA30_CLK_NOR 4264/* 43 */65#define TEGRA30_CLK_SBC2 4466/* 45 */67#define TEGRA30_CLK_SBC3 4668#define TEGRA30_CLK_I2C5 4769#define TEGRA30_CLK_DSIA 4870/* 49 (register bit affects cve and tvo) */71#define TEGRA30_CLK_MIPI 5072#define TEGRA30_CLK_HDMI 5173#define TEGRA30_CLK_CSI 5274#define TEGRA30_CLK_TVDAC 5375#define TEGRA30_CLK_I2C2 5476#define TEGRA30_CLK_UARTC 5577/* 56 */78#define TEGRA30_CLK_EMC 5779#define TEGRA30_CLK_USB2 5880#define TEGRA30_CLK_USB3 5981#define TEGRA30_CLK_MPE 6082#define TEGRA30_CLK_VDE 6183#define TEGRA30_CLK_BSEA 6284#define TEGRA30_CLK_BSEV 6385 86#define TEGRA30_CLK_SPEEDO 6487#define TEGRA30_CLK_UARTD 6588#define TEGRA30_CLK_UARTE 6689#define TEGRA30_CLK_I2C3 6790#define TEGRA30_CLK_SBC4 6891#define TEGRA30_CLK_SDMMC3 6992#define TEGRA30_CLK_PCIE 7093#define TEGRA30_CLK_OWR 7194#define TEGRA30_CLK_AFI 7295#define TEGRA30_CLK_CSITE 7396/* 74 */97#define TEGRA30_CLK_AVPUCQ 7598#define TEGRA30_CLK_LA 7699/* 77 */100/* 78 */101#define TEGRA30_CLK_DTV 79102#define TEGRA30_CLK_NDSPEED 80103#define TEGRA30_CLK_I2CSLOW 81104#define TEGRA30_CLK_DSIB 82105/* 83 */106#define TEGRA30_CLK_IRAMA 84107#define TEGRA30_CLK_IRAMB 85108#define TEGRA30_CLK_IRAMC 86109#define TEGRA30_CLK_IRAMD 87110#define TEGRA30_CLK_CRAM2 88111/* 89 */112#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */113/* 91 */114#define TEGRA30_CLK_CSUS 92115#define TEGRA30_CLK_CDEV2 93116#define TEGRA30_CLK_CDEV1 94117/* 95 */118 119#define TEGRA30_CLK_CPU_G 96120#define TEGRA30_CLK_CPU_LP 97121#define TEGRA30_CLK_GR3D2 98122#define TEGRA30_CLK_MSELECT 99123#define TEGRA30_CLK_TSENSOR 100124#define TEGRA30_CLK_I2S3 101125#define TEGRA30_CLK_I2S4 102126#define TEGRA30_CLK_I2C4 103127#define TEGRA30_CLK_SBC5 104128#define TEGRA30_CLK_SBC6 105129#define TEGRA30_CLK_D_AUDIO 106130#define TEGRA30_CLK_APBIF 107131#define TEGRA30_CLK_DAM0 108132#define TEGRA30_CLK_DAM1 109133#define TEGRA30_CLK_DAM2 110134#define TEGRA30_CLK_HDA2CODEC_2X 111135#define TEGRA30_CLK_ATOMICS 112136#define TEGRA30_CLK_AUDIO0_2X 113137#define TEGRA30_CLK_AUDIO1_2X 114138#define TEGRA30_CLK_AUDIO2_2X 115139#define TEGRA30_CLK_AUDIO3_2X 116140#define TEGRA30_CLK_AUDIO4_2X 117141#define TEGRA30_CLK_SPDIF_2X 118142#define TEGRA30_CLK_ACTMON 119143#define TEGRA30_CLK_EXTERN1 120144#define TEGRA30_CLK_EXTERN2 121145#define TEGRA30_CLK_EXTERN3 122146#define TEGRA30_CLK_SATA_OOB 123147#define TEGRA30_CLK_SATA 124148#define TEGRA30_CLK_HDA 125149/* 126 */150#define TEGRA30_CLK_SE 127151 152#define TEGRA30_CLK_HDA2HDMI 128153#define TEGRA30_CLK_SATA_COLD 129154/* 130 */155/* 131 */156/* 132 */157/* 133 */158/* 134 */159/* 135 */160#define TEGRA30_CLK_CEC 136161/* 137 */162/* 138 */163/* 139 */164/* 140 */165/* 141 */166/* 142 */167/* 143 */168/* 144 */169/* 145 */170/* 146 */171/* 147 */172/* 148 */173/* 149 */174/* 150 */175/* 151 */176/* 152 */177/* 153 */178/* 154 */179/* 155 */180/* 156 */181/* 157 */182/* 158 */183/* 159 */184 185#define TEGRA30_CLK_UARTB 160186#define TEGRA30_CLK_VFIR 161187#define TEGRA30_CLK_SPDIF_IN 162188#define TEGRA30_CLK_SPDIF_OUT 163189#define TEGRA30_CLK_VI 164190#define TEGRA30_CLK_VI_SENSOR 165191#define TEGRA30_CLK_FUSE 166192#define TEGRA30_CLK_FUSE_BURN 167193#define TEGRA30_CLK_CVE 168194#define TEGRA30_CLK_TVO 169195#define TEGRA30_CLK_CLK_32K 170196#define TEGRA30_CLK_CLK_M 171197#define TEGRA30_CLK_CLK_M_DIV2 172198#define TEGRA30_CLK_CLK_M_DIV4 173199#define TEGRA30_CLK_OSC_DIV2 172200#define TEGRA30_CLK_OSC_DIV4 173201#define TEGRA30_CLK_PLL_REF 174202#define TEGRA30_CLK_PLL_C 175203#define TEGRA30_CLK_PLL_C_OUT1 176204#define TEGRA30_CLK_PLL_M 177205#define TEGRA30_CLK_PLL_M_OUT1 178206#define TEGRA30_CLK_PLL_P 179207#define TEGRA30_CLK_PLL_P_OUT1 180208#define TEGRA30_CLK_PLL_P_OUT2 181209#define TEGRA30_CLK_PLL_P_OUT3 182210#define TEGRA30_CLK_PLL_P_OUT4 183211#define TEGRA30_CLK_PLL_A 184212#define TEGRA30_CLK_PLL_A_OUT0 185213#define TEGRA30_CLK_PLL_D 186214#define TEGRA30_CLK_PLL_D_OUT0 187215#define TEGRA30_CLK_PLL_D2 188216#define TEGRA30_CLK_PLL_D2_OUT0 189217#define TEGRA30_CLK_PLL_U 190218#define TEGRA30_CLK_PLL_X 191219 220#define TEGRA30_CLK_PLL_X_OUT0 192221#define TEGRA30_CLK_PLL_E 193222#define TEGRA30_CLK_SPDIF_IN_SYNC 194223#define TEGRA30_CLK_I2S0_SYNC 195224#define TEGRA30_CLK_I2S1_SYNC 196225#define TEGRA30_CLK_I2S2_SYNC 197226#define TEGRA30_CLK_I2S3_SYNC 198227#define TEGRA30_CLK_I2S4_SYNC 199228#define TEGRA30_CLK_VIMCLK_SYNC 200229#define TEGRA30_CLK_AUDIO0 201230#define TEGRA30_CLK_AUDIO1 202231#define TEGRA30_CLK_AUDIO2 203232#define TEGRA30_CLK_AUDIO3 204233#define TEGRA30_CLK_AUDIO4 205234#define TEGRA30_CLK_SPDIF 206235/* 207 */236/* 208 */237/* 209 */238#define TEGRA30_CLK_SCLK 210239/* 211 */240#define TEGRA30_CLK_CCLK_G 212241#define TEGRA30_CLK_CCLK_LP 213242#define TEGRA30_CLK_TWD 214243#define TEGRA30_CLK_CML0 215244#define TEGRA30_CLK_CML1 216245#define TEGRA30_CLK_HCLK 217246#define TEGRA30_CLK_PCLK 218247/* 219 */248#define TEGRA30_CLK_OSC 220249/* 221 */250/* 222 */251/* 223 */252 253/* 288 */254/* 289 */255/* 290 */256/* 291 */257/* 292 */258/* 293 */259/* 294 */260/* 295 */261/* 296 */262/* 297 */263/* 298 */264/* 299 */265/* 300 */266/* 301 */267/* 302 */268#define TEGRA30_CLK_AUDIO0_MUX 303269#define TEGRA30_CLK_AUDIO1_MUX 304270#define TEGRA30_CLK_AUDIO2_MUX 305271#define TEGRA30_CLK_AUDIO3_MUX 306272#define TEGRA30_CLK_AUDIO4_MUX 307273#define TEGRA30_CLK_SPDIF_MUX 308274#define TEGRA30_CLK_CLK_MAX 309275 276#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */277