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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (C) 2023 Vivo Communication Technology Co. Ltd.4 * Authors: Yangtao Li <frank.li@vivo.com>5 */6 7#ifndef _DT_BINDINGS_CLK_TH1520_H_8#define _DT_BINDINGS_CLK_TH1520_H_9 10#define CLK_CPU_PLL0 011#define CLK_CPU_PLL1 112#define CLK_GMAC_PLL 213#define CLK_VIDEO_PLL 314#define CLK_DPU0_PLL 415#define CLK_DPU1_PLL 516#define CLK_TEE_PLL 617#define CLK_C910_I0 718#define CLK_C910 819#define CLK_BROM 920#define CLK_BMU 1021#define CLK_AHB2_CPUSYS_HCLK 1122#define CLK_APB3_CPUSYS_PCLK 1223#define CLK_AXI4_CPUSYS2_ACLK 1324#define CLK_AON2CPU_A2X 1425#define CLK_X2X_CPUSYS 1526#define CLK_AXI_ACLK 1627#define CLK_CPU2AON_X2H 1728#define CLK_PERI_AHB_HCLK 1829#define CLK_CPU2PERI_X2H 1930#define CLK_PERI_APB_PCLK 2031#define CLK_PERI2APB_PCLK 2132#define CLK_PERISYS_APB1_HCLK 2233#define CLK_PERISYS_APB2_HCLK 2334#define CLK_PERISYS_APB3_HCLK 2435#define CLK_PERISYS_APB4_HCLK 2536#define CLK_OSC12M 2637#define CLK_OUT1 2738#define CLK_OUT2 2839#define CLK_OUT3 2940#define CLK_OUT4 3041#define CLK_APB_PCLK 3142#define CLK_NPU 3243#define CLK_NPU_AXI 3344#define CLK_VI 3445#define CLK_VI_AHB 3546#define CLK_VO_AXI 3647#define CLK_VP_APB 3748#define CLK_VP_AXI 3849#define CLK_CPU2VP 3950#define CLK_VENC 4051#define CLK_DPU0 4152#define CLK_DPU1 4253#define CLK_EMMC_SDIO 4354#define CLK_GMAC1 4455#define CLK_PADCTRL1 4556#define CLK_DSMART 4657#define CLK_PADCTRL0 4758#define CLK_GMAC_AXI 4859#define CLK_GPIO3 4960#define CLK_GMAC0 5061#define CLK_PWM 5162#define CLK_QSPI0 5263#define CLK_QSPI1 5364#define CLK_SPI 5465#define CLK_UART0_PCLK 5566#define CLK_UART1_PCLK 5667#define CLK_UART2_PCLK 5768#define CLK_UART3_PCLK 5869#define CLK_UART4_PCLK 5970#define CLK_UART5_PCLK 6071#define CLK_GPIO0 6172#define CLK_GPIO1 6273#define CLK_GPIO2 6374#define CLK_I2C0 6475#define CLK_I2C1 6576#define CLK_I2C2 6677#define CLK_I2C3 6778#define CLK_I2C4 6879#define CLK_I2C5 6980#define CLK_SPINLOCK 7081#define CLK_DMA 7182#define CLK_MBOX0 7283#define CLK_MBOX1 7384#define CLK_MBOX2 7485#define CLK_MBOX3 7586#define CLK_WDT0 7687#define CLK_WDT1 7788#define CLK_TIMER0 7889#define CLK_TIMER1 7990#define CLK_SRAM0 8091#define CLK_SRAM1 8192#define CLK_SRAM2 8293#define CLK_SRAM3 8394#define CLK_PLL_GMAC_100M 8495#define CLK_UART_SCLK 8596#endif97