124 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (C) 2019 Xilinx Inc.4 *5 */6 7#ifndef _DT_BINDINGS_CLK_VERSAL_H8#define _DT_BINDINGS_CLK_VERSAL_H9 10#define PMC_PLL 111#define APU_PLL 212#define RPU_PLL 313#define CPM_PLL 414#define NOC_PLL 515#define PLL_MAX 616#define PMC_PRESRC 717#define PMC_POSTCLK 818#define PMC_PLL_OUT 919#define PPLL 1020#define NOC_PRESRC 1121#define NOC_POSTCLK 1222#define NOC_PLL_OUT 1323#define NPLL 1424#define APU_PRESRC 1525#define APU_POSTCLK 1626#define APU_PLL_OUT 1727#define APLL 1828#define RPU_PRESRC 1929#define RPU_POSTCLK 2030#define RPU_PLL_OUT 2131#define RPLL 2232#define CPM_PRESRC 2333#define CPM_POSTCLK 2434#define CPM_PLL_OUT 2535#define CPLL 2636#define PPLL_TO_XPD 2737#define NPLL_TO_XPD 2838#define APLL_TO_XPD 2939#define RPLL_TO_XPD 3040#define EFUSE_REF 3141#define SYSMON_REF 3242#define IRO_SUSPEND_REF 3343#define USB_SUSPEND 3444#define SWITCH_TIMEOUT 3545#define RCLK_PMC 3646#define RCLK_LPD 3747#define WDT 3848#define TTC0 3949#define TTC1 4050#define TTC2 4151#define TTC3 4252#define GEM_TSU 4353#define GEM_TSU_LB 4454#define MUXED_IRO_DIV2 4555#define MUXED_IRO_DIV4 4656#define PSM_REF 4757#define GEM0_RX 4858#define GEM0_TX 4959#define GEM1_RX 5060#define GEM1_TX 5161#define CPM_CORE_REF 5262#define CPM_LSBUS_REF 5363#define CPM_DBG_REF 5464#define CPM_AUX0_REF 5565#define CPM_AUX1_REF 5666#define QSPI_REF 5767#define OSPI_REF 5868#define SDIO0_REF 5969#define SDIO1_REF 6070#define PMC_LSBUS_REF 6171#define I2C_REF 6272#define TEST_PATTERN_REF 6373#define DFT_OSC_REF 6474#define PMC_PL0_REF 6575#define PMC_PL1_REF 6676#define PMC_PL2_REF 6777#define PMC_PL3_REF 6878#define CFU_REF 6979#define SPARE_REF 7080#define NPI_REF 7181#define HSM0_REF 7282#define HSM1_REF 7383#define SD_DLL_REF 7484#define FPD_TOP_SWITCH 7585#define FPD_LSBUS 7686#define ACPU 7787#define DBG_TRACE 7888#define DBG_FPD 7989#define LPD_TOP_SWITCH 8090#define ADMA 8191#define LPD_LSBUS 8292#define CPU_R5 8393#define CPU_R5_CORE 8494#define CPU_R5_OCM 8595#define CPU_R5_OCM2 8696#define IOU_SWITCH 8797#define GEM0_REF 8898#define GEM1_REF 8999#define GEM_TSU_REF 90100#define USB0_BUS_REF 91101#define UART0_REF 92102#define UART1_REF 93103#define SPI0_REF 94104#define SPI1_REF 95105#define CAN0_REF 96106#define CAN1_REF 97107#define I2C0_REF 98108#define I2C1_REF 99109#define DBG_LPD 100110#define TIMESTAMP_REF 101111#define DBG_TSTMP 102112#define CPM_TOPSW_REF 103113#define USB3_DUAL_REF 104114#define OUTCLK_MAX 105115#define REF_CLK 106116#define PL_ALT_REF_CLK 107117#define MUXED_IRO 108118#define PL_EXT 109119#define PL_LB 110120#define MIO_50_OR_51 111121#define MIO_24_OR_25 112122 123#endif124